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TLC555CPWR 数据表(PDF) 14 Page - Texas Instruments |
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TLC555CPWR 数据表(HTML) 14 Page - Texas Instruments |
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14 / 42 page ![]() R1 R S 1 THRES R R R TRIG 2 1 GND DISCH 7 3 OUT 6 VDD 8 5 CONT RESET 4 14 TLC555 SLFS043I – SEPTEMBER 1983 – REVISED JULY 2019 www.ti.com Product Folder Links: TLC555 Submit Documentation Feedback Copyright © 1983–2019, Texas Instruments Incorporated 7 Detailed Description 7.1 Overview The TLC555 is a precision timing device used for general-purpose timing applications up to 2.1 MHz. All inputs are level sensitive not edge triggered inputs. 7.2 Functional Block Diagram Pin numbers are for all packages except the PW and FK package. RESET can override TRIG, which can override THRES (when CONT pin is 2/3 VDD). The resistance of “R" resistors vary with VDD and temperature. The resistors match each other very well across VDD and temperature for a temperature stable control voltage ratio. 7.3 Feature Description 7.3.1 Monostable Operation For monostable operation, any of these timers can be connected as shown in Figure 9. If the output is low, application of a negative-going pulse to the trigger (TRIG) sets the internal latch; the output goes high, and discharge pin (DISCH) becomes open drain. Capacitor C then is charged through RA until the voltage across the capacitor reaches the threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the threshold comparator resets the internal latch, the output goes low, the discharge pin goes low which quickly discharges capacitor C. |
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