TLC555CPWR datasheet(22/42 Pages) TI

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Control Voltage (V)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

100

D015

Clock period = 1 RC

Clock period = 2.5 RC

TLC555

SLFS043I – SEPTEMBER 1983 – REVISED JULY 2019

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Typical Applications (continued)

8.2.2.1 Design Requirements

The clock input must have VOL and VOH levels that are less than and greater than 1/3 VDD, respectively. Clock

input VOL time must be less than minimum output high time, therefore a high (positive) duty cycle clock is

recommended. Minimum recommended modulation voltage is 1 V. Lower CONT voltage can greatly increase

threshold comparator’s propagation delay and storage time. The application must be tolerant of a nonlinear

transfer function; the relationship between modulation input and pulse width is not linear because the capacitor

charge is RC based with an negative exponential curve.

8.2.2.2 Detailed Design Procedure

Choose RA and C so that RA × C is same or less than clock input period. Figure 21 shows the non linear

relationship between control voltage and output duty cycle. Duty cycle is function of control voltage and clock

period relative to RC time constant.

8.2.2.3 Application Curve

Figure 21. Pulse-Width-Modulation vs Control Voltage

Clock Duty Cycle 98%, VDD = 5 V

8.2.3 Pulse-Position Modulation

As shown in Figure 22, any of these timers can be used as a pulse-position modulator. This application

modulates the threshold voltage and thereby the time delay of a free-running oscillator. Figure 23 and Figure 24

shows the output frequency and duty cycle versus control voltage.

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