ADP1032ACPZ-2-R7 datasheet(24/37 Pages) AD

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ADP1032

Data Sheet

Rev. 0 | Page 24 of 37

FLYBACK REGULATOR

Flyback Regulator Operation

The flyback regulator in the ADP1032 generates an isolated output

supply rail that can be programmed from 6 V to 28 V for the

adjustable output version or 24 V for the factory programmable

fixed output versions. The flyback regulator adopts current mode

control, resulting in a fast, inner current controlled loop that

regulates the peak inductor current and a slower outer loop via

an isolated iCoupler channel that adjusts the current controlled

loop to define a regulated output voltage. When the high voltage

switch is on, the diode on the secondary side of the transformer

is reverse biased, which causes an increase in the current in the

primary inductance of the transformer and is stored as energy.

When the switch turns off, the diode becomes forward biased,

and energy stored in the transformer is transferred to the load.

Traditionally, in an isolated flyback regulator, a discrete opto-

coupler is used in the feedback path to transmit the signal from

the secondary side to the primary side. However, the current

transfer ratio (CTR) of the optocouplers degrades over time and

over temperature. Therefore, the optocoupler must be replaced

every 5 years to 10 years. The ADP1032 eliminates the use of an

optocoupler and the associated problems by integrating Analog

Devices, Inc., iCoupler technology for feedback, which reduces

system cost, PCB area, and complexity, while improving system

reliability without the issue of CTR degradation.

The flyback regulator uses a transformer with a single primary

and secondary winding. This configuration is possible because

Coupler technology is used to send an isolated control signal to

the primary side controller so that a primary sense winding is

not required. In addition, because the secondary rail is generated

using a high efficiency switching regulator, extra secondary

windings are not required. This approach offers a number of

advantages over an alternative multiwinding solution, such as

the following:



A smaller transformer solution size due to a lower number

of turns required on the core and a fewer number of pins.



Each output can be independently set. The multitap

approach requires a custom multitap transformer for

different output voltage combinations.



Outputs are more accurate because the outputs do not rely

on the discrete ratios between the transformer windings.



Output accuracy is unaffected by load changes on each rail.

Power Saving Mode (PSM)

During light load operation, the regulators can skip pulses to

maintain output voltage regulation. Therefore, no minimum

load is required. Skipping pulses increases the device efficiency

but results in larger output ripple.

Flyback Undervoltage Lockout (UVLO)

The UVLO circuitry monitors the VINP pin voltage level. If the

input voltage drops below the VUVLO_VINP(FALL) threshold, the

flyback regulator turns off. After the VINP pin voltage rises

above the VUVLO_VINP (RISE) threshold, the soft start period

initiates, and the flyback regulator enables.

Flyback Regulator Precision Enable Control

The flyback regulator in the ADP1032 features a precision

enable circuit with an accurate reference voltage. If the voltage

at the EN pin rises above the VEN_RISING threshold, the flyback

regulator soft start period initiates, and the regulator enables. If

the EN pin voltage falls below the VEN_RISING − VEN_HYST threshold,

the flyback regulator turns off.

Flyback Regulator Soft Start

The flyback regulator includes a soft start function that limits

the inrush current from the supply and ramps up the output

voltage in a controlled manner. The flyback regulator soft start

period initiates when the voltage at the EN pin rises above the

VEN_RISING threshold.

Flyback Slew Rate Control

The flyback regulator employs programmable output driver slew

rate control circuitry. This circuitry adjusts the slew rate of the

switching node as shown in Figure 67, where lower EMI and

reduced ringing can be achieved at slightly lower efficiency

operation and vice versa. To program the slew rate, connect the

SLEW pin to the VINP pin for normal mode, to the GNDP pin

for slow mode, or leave it open for fast mode.

Slew rate control causes a trade-off between efficiency and

low EMI.

FASTEST

SLOWEST

Figure 67. Switching Node at Various Slew Rate Settings

Table 11. Slew Rate Settings

SLEW Pin

Connection

Slew Rate

Comment

GNDP

Slow

Lowest EMI

VINP

Normal

Optimized efficiency and EMI

Unconnected

Fast

Highest efficiency

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