ADP1032ACPZ-2-R7 datasheet(27/37 Pages) AD

27 / 37 page

Data Sheet

ADP1032

Rev. 0 | Page 27 of 37

SSS

SCK, SI, MI

MCK, MO, SO

HIGH IMPEDANCE

ADD A PULL HIGH OR PULL LOW RESISTOR

TO HAVE A KNOWN STATE WHEN MSS IS HIGH.

LATENCY = MSS FALLING EDGE TO SCK, SI, MI STARTS SENDING DATA (EXIT TO HIGH IMPEDANCE MODE).

tPW = MCK, MO, SO PULSE WIDTH.

tP1 = MSS TO SSS PROPAGATION DELAY.

tP2 = MCK TO SCK, MO TO SI, SO TO MI PROPAGATION DELAY.

tP3 = MSS RISING EDGE TO SCK, SI, MI RETURN TO HIGH IMPEDANCE STATE. SAME AS tP1.

MSS

tP1

tP2

tPW

SPI

ACTIVATION

(LATENCY)

SPI TRANSMIT

tP3

Figure 70. SPI Isolators Timing Diagram

MSS

MCK

MSS1

MSS4

MSS3

MSS2

SSS

SCK

MCK

TO CHANNEL 5

THROUGH

CHANNEL 8

MSS

MCK

CHANNEL 2

MSS

MCK

CHANNEL 3

MSS

MCK

CHANNEL 4

CHANNEL 1

SSS

SCK

SSS

SCK

SSS

SCK

Figure 71. Multichannel SPI Muxing Scheme

The MI, SCK, and SI outputs are also tristated when MSS is high

(see Table 14) to allow a more flexible design and to avoid the

requirement for external multiplexing of MI in a multichannel

system. Figure 71 shows how the SPI busses from multiple

ADP1032 devices can be connected together.

Table 14. SPI MSS Gating

Parameter

MSS High

MSS Low

SSS

High

Low

SCK

Tristate

MCK

Tristate

Connect a pull-up or pull-down resistor to MI, SCK, and SI to

pull these pins to the desired logic state when MSS is high.

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