ADP1032ACPZ-2-R7 datasheet(26/37 Pages) AD

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ADP1032

Data Sheet

Rev. 0 | Page 26 of 37

POWER-UP SEQUENCE

The power-up sequence is as follows (see Figure 68):

The flyback regulator powers up first (see Label 1 in

Figure 68).

When VOUT1 rises above the lower power-good threshold

(VPG_FLYBACK_LL), the buck regulator turns on (see Label 2 in

Figure 68).

When the buck regulator output (VOUT2) rises above the

lower power-good threshold (VPG_BUCK_LL), the PWRGD is

driven high (see 3 in Figure 68).

If any of the two analog supplies move outside the

power-good threshold ranges, PWRGD drives low after a

short deglitch delay (see 4 in Figure 68).

HIGH

LOW

PWRGD

VOUT2

VINP

VOUT1

VPG_FLYBACK_UL

VPG_FLYBACK_LL

VPG_BUCK_LL

Figure 68. Power Sequencing and PWRGD

OSCILLATOR AND SYNCHRONIZATION

A phase-locked loop (PLL)-based oscillator generates the internal

clock for the flyback and buck regulators and offers an internally

generated frequency or external clock synchronization. Connect

the SYNC pin as described in Table 12 to configure the switching

frequency. For external synchronization, connect the SYNC pin to

a suitable clock source. The PLL locks to an input clock within

the range specified by fSYNC.

Table 12. Sync Pin Functionality

SYNC Pin State

Switching Frequency (fSW)

Flyback

Buck

Low or High

250 kHz

125 kHz

350 kHz to 750 kHz

fSYNC/2

fSYNC/4

THERMAL SHUTDOWN

If the ADP1032 junction temperature rises above TSHDN, the

thermal shutdown circuit turns the flyback regulator off.

Extreme junction temperatures can be the result of prolonged

high current operation, poor circuit board design, and/or high

ambient temperatures. When thermal shutdown occurs, hysteresis

is included so that the ADP1032 does not return to operation until

the on-chip temperature drops below TSHDN − THYS. When resuming

from thermal shutdown, the ADP1032 performs a soft start.

DATA ISOLATION

High Speed SPI Channels

The ADP1032 has four high speed channels. The first three,

CLK, MI/SO, and MO/SI (the slash indicates the connection of

the input and output forming a datapath across the isolator that

corresponds to an SPI bus signal), are optimized for low

propagation delay. With a maximum propagation delay of 15 ns,

the ADP1032 supports read and write clock rates up to 16.6 MHz

in the standard 4-wire SPI. However, in practice, the maximum

clock rate of 16.6 MHz is reduced as a result of the delays added

across the total ground trip of the signal.

The relationship between the SPI signal paths, the ADP1032 pin

mnemonics, and the data directions are detailed in Table 13.

Table 13. Correspondence of the Pin Mnemonics to the SPI

Signal Path Names

SPI Signal Path

Master Side

Data Direction

Slave Side

CLK

MCK

→

SCK

MO/SI

→

MI/SO

←

MSS

→

SSS

The datapaths are SPI mode agnostic. The CLK and MO/SI SPI

datapaths are optimized for propagation delay and channel to

channel matching. The MI/SO SPI datapath is optimized for

propagation delay. The device does not synchronize to the clock

channels. Therefore, there are no constraints on the clock

polarity or timing with respect to the data lines.

Slave select (SS) is an active low signal. To save power in a

multichannel system, SS puts the other SPI isolator channels in

a low power state when the channels are not in use (SS = high),

and these channels are only active when required, which is when

SS is low. The clock and data channels are gated to the SS as shown

in Figure 69. However, this power saving mode adds 100 ns of

latency. This latency is the time required for the internal circuitry

to wake up from the low power state and to start transmitting

data to the isolation barrier. Conversely, the latency is the delay

from the falling edge of MSS to the first clock edge or data edge

that appears on the slave side, as shown in Figure 70.

DECODE

ENCODE

DECODE

ENCODE

DECODE

ENCODE

DECODE

MSS

MCK

SSS

SCK

Figure 69. High Speed Data Isolation Channel Gating

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