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ADP1074WARWZ-R7 数据表(PDF) 17 Page - Analog Devices |
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ADP1074WARWZ-R7 数据表(HTML) 17 Page - Analog Devices |
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17 / 32 page ![]() Data Sheet ADP1074 Rev. D | Page 17 of 32 DETAILED BLOCK DIAGRAM Figure 13 shows a detailed block diagram of the ADP1074. VREG1 NGATE VIN CS 8V LDO DRV OSCILLATOR RT Q S R LOGIC AGND2 5V LDO VDD2 PGOOD THERMAL LIMIT 1.10V LOGIC OVP VREF2 VREG2 VREF 1.2V VREG SR1 SR2 PWM LOGIC CONTROL PGATE DRV LOGIC AND DEAD TIME CTRL PGND2 PGND1 COMP AGND1 14V DRV VREG2 VREG2 VREG2 DRV MODE DMAX SS1 OV LLM THRESHOLD COMP DC 1.36V COMP FB gm AMPLIFIER 1.2VREF VREG2 CLAMP MAXIMUM CLAMP MINIMUM SS2 OCP RECOVERY SLOPE RAMP SYNC fOSC EN 1.2V 4µA 1µA Tx VREG OV BIAS OC THRESHOLD DETECT SECONDARY SIDE UVLO AND HANDOVER CONTROL FROM PRIMARY HANDOVER TO SECONDARY 1.36V Rx Tx Rx OV DETECT 6µA Figure 13. Detailed Block Diagram |
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