ADP1074WARWZ-R7 datasheet(20/32 Pages) AD

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ADP1074

Data Sheet

Rev. D | Page 20 of 32

The COMP node is clamped to a lower and higher level of

approximately 0.7 V and 2.52 V, respectively. This is

representative of the CS range from 0 mV to 120 mV.

SLOPE COMPENSATION

For a peak current mode controller with duty cycle higher than

50%, slope compensation is necessary for a stable operation. To

set up an external compensation in the ADP1074, connect the

external RRAMP resistor (see Figure 25) between CS and the current

sense resistor, RSENSE, to set up the slope voltage ramp for the

control signal. It is important to sense the signal differentially.

See the Layout Guidelines section for more details.

An internal ramp current starts from 0 μA at the minimum duty

cycle (that is, the beginning of the switching period) and increases

linearly toward a maximum of 20 μA at the end of the switching

period. The slope of the voltage ramp is the ramp current times

RRAMP. RRAMP is sized using the following equation:

20 μA

OUT

SENSE

RAMP

VN2

LN1





where:

k = 0.5 for nominal cases and k = 1 for deadbeat control.

VOUT is the desired output voltage.

L is the output inductor.

N1 and N2 are the primary and secondary turns of the

transformer.

tS is the switching period.

INPUT/OUTPUT CURRENT-LIMIT PROTECTION

There is no direct current-limit sensing circuit on the secondary;

the output current limit is indirectly limited by the cycle-by-cycle

primary side current limit of 120 mV on the CS pin.

The input peak current limit is set by connecting a sense

resistor, RSENSE, from the source of the main MOSFET to

PGND1 (see Figure 25), and the sensed voltage appears at the

CS pin. To generate the slope-comp ramp, insert the slope

compensation resistor, RRAMP, between CS and RSENSE.

The CS current limit, VCSLIM, is internally set to 120 mV. Calculate

the RSENSE value by

20 μA

CSLIM

RAMP

SENSE

PKPRI





where:

VCSLIM is the CS current limit.

IPKPRI is the primary peak current.

When the sensed input peak current is above the CS limit

threshold, the controller operates in the cycle-by-cycle constant

current-limit mode for 1.5 ms. Then the controller immediately

shuts down the primary and secondary drivers. The controller

then goes into hiccup mode for the next 40 ms and restarts the

soft start sequence after this timeout period.

The slope ramp can affect the accuracy of the current-limit

threshold because the voltage drop across RRAMP contributes to

the inaccuracy of the peak current limit. For instance, if the

added slope ramp voltage is 20% of the current-limit threshold,

the actual input peak current limit can be off by as much as

20% depending on where the peak current-limit threshold is

tripped during the on cycle. In the event of an output short

circuit, the controller treats this condition as an overcurrent

event and enters the 40 ms hiccup mode.

Under certain conditions, the ADP1074 exits OCP hiccup

mode. In these conditions, the COMP pin is at the maximum

clamp level, but the device does not enter hiccup mode.

However, it is guaranteed that the PWMs are terminated

whenever the CS maximum threshold is reached. The condition

under which the ADP1074 skips entering hiccup mode is when

VDD2 is powered through an auxiliary winding and an output

short circuit occurs that results in the FB pin having a voltage

that is <300 mV. This event is more prominent at high

temperatures (>85°C), and can be exacerbated at higher

temperatures.

The root cause of the device exiting hiccup mode is due to the

effect that the OCP hiccup mode feature has on the SS2 pin.

During OCP recovery, the SS2 pin tracks the FB pin and attempts

a soft start from the precharge sequence. During the time when

SS2 tracks the FB pin, the SS2 pin voltage can be less than the

FB pin for a short interval, which causes the COMP pin (output

of the gm amplifier) to momentarily dip below the maximum

COMP pin clamp level. This event means that the current limit

required for the next few switching periods is less than the maxi-

mum threshold and puts the device out of hiccup mode because

the ADP1074 fails to register 1.25 ms worth of consecutive

overcurrent cycles.

The following scenarios guarantee OCP hiccup mode based on

the configuration of the VDD2 power supply:

When VDD2 is powered directly from the output voltage,

if a short circuit occurs on the output terminals of the load

after steady state regulation is achieved, the voltage of the

VDD2 pin is less than the UVLO, and the device enters

hiccup mode for 200 ms, similar to the hiccup time described

in the Remote System Reset section.

When VDD2 is powered through auxiliary winding or

another configuration, when a short circuit occurs on the

output terminals, the auxiliary winding is not shorted and

maintains a positive voltage above the UVLO threshold of

the VDD2 pin. To enter hiccup mode, it is recommended to

use the circuit shown in Figure 15. The circuit operates as

follows: when the output voltage goes low due to a short

circuit, the D1 diode turns on, which pulls the base of the

bipolar junction transistor low, shutting off VDD2. The

system then enters hiccup mode, as described in the

Remote System Reset section.

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