ADP1074ARWZ-R7 datasheet(23/32 Pages) AD

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Data Sheet

ADP1074

Rev. D | Page 23 of 32

If the load is further reduced and the COMP pin voltage becomes

equal to the minimum COMP clamp level, the ADP1074 enters

pulse skip mode.

The NGATE delay time settings shown in Figure 17 remain

unchanged in LLM operation. Use the following formula to set

up the light load mode threshold:

MODE

GAIN

LLM

PEAK

MODE







where:

IPEAK_LLM is the peak primary current at the light load condition.

CSGAIN = 12.5.

IMODE is the current flowing out of the MODE pin.

For a forced CCM operation, connect MODE to AGND2. In

this case, pulse skipping is disabled.

Note also that when the system enters light load mode, the

synchronous rectifiers terminate at the falling edge of SR1. This

termination facilitates the prevention of the PWM at a negative

current, which can cause a spike in voltage that can damage the

synchronous FET.

EXTERNAL START-UP CIRCUIT

For input voltages higher than 36 V, where the power

dissipation in the internal 8 V LDO can be significant, the use of

an external start-up circuit is recommended. (See Figure 18 for

an example.) In this case, the VIN and VREG1 pins are shorted

together and connect to the output of the start-up circuit.

Because the input pre-enable bias current, the (VIN + VREG1)

start-up current, is approximately 160 μA, the output of the start-

up circuit must be able to provide this level of current to

perform a soft start. The auxiliary winding then provides the

bias voltage, shutting off the start-up circuit after soft start

completes.

8V LDO

START-UP

CIRCUIT

ADP1074

1µA

4µA

LOGIC

VREF

1.2V

VIN

VAUX1

VREG UVLO

VIN

VREG1

HYSTERESIS

GENERATOR

Figure 18. Precision EN Circuit Connection with an External Start-Up Circuit

A fast start-up circuit is shown in Figure 19. This circuit requires

two components: a Zener diode, which sets up the start-up

voltage at the VIN and VREG1 pin, and a negative-positive-

negative (NPN) transistor, which sets up a fast current path for

charging up the start-up capacitor, C1. The start-up current

through R1 must be more than 160 μA, which is the minimum

specified start-up current, and it is recommended that the start-

up voltage at VREG1 and VIN be approximately 8 V to 13 V.

The auxiliary winding then provides the bias voltage, shutting

off the NPN transistor after soft start completes.

ADP1074

LDO

2.2µF

8.7V TO 11V

VIN

14V

VAUX = 8V TO 13V

FROM

AUXILLIARY

WINDING

VREG1

Figure 19. Fast Start-Up Circuit

SOFT STOP

The ADP1074 employs a soft stop feature that brings the

output voltage gradually down to zero by using the SS2 pin as a

reference. During the soft stop procedure, the SS2 pin is discharged

to zero by a current sink of approximately 1.5 times the value

during closed-loop soft start.

When the voltage at EN drops below the EN threshold, the SR1

and SR2 secondary drivers shut off immediately, and the primary

NGATE pulse width gradually decreases the duty cycle from the

last known condition to the minimum pulse width and down to

zero, causing the output voltage to decrease. The soft stop feature

prevents any reverse current when the controller is shut down.

When the output voltage decreases below the VDD2 UVLO

threshold, there is no transmission of the COMP signal to the

primary side. Therefore, the output voltage continues to decrease

at the rate at which the load current discharges the output

capacitor.

When the load is at a minimum or at no load, the output voltage

does not discharge because any reduction in duty cycle or

current limit does not discharge the output voltage linearly.

POWER GOOD

The PGOOD pin is an open-drain N-channel metal-oxide

semiconductor (nMOS), which is off in fault conditions.

Connect a pull-up resistor between PGOOD and VREG2 or to

an external power supply less than 5.5 V.

To toggle PGOOD, the fault voltage on the FB pin and the OVP

pin must exceed the overvoltage threshold of 1.36 V. PGOOD

also toggles if the FB pin voltage drops 100 mV below the

nominal of 1.2 V, that is, to 1.1 V.

PGOOD toggles again after the output voltage crosses the

PGOOD hysteresis voltage of 36 mV. PGOOD becomes active

after a delay of 5 μs for an FB pin fault and after 90 ns for an

OVP pin fault.

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