PCF8564A datasheet(38/59 Pages) NXP

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PCA85063A

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Product data sheet

Rev. 4 — 30 March 2018

38 of 59

NXP Semiconductors

PCA85063A

Automotive Real-Time Clock/calendar with alarm function and I2C-bus

[1]

For reliable oscillator start-up at power-on use VDD greater than 1.2 V. If powered up at 0.9 V the oscillator will start but it might be a bit

slow, especially if at high temperature. Normally the power supply is not 0.9 V at start-up and only comes at the end of battery

discharge. VDD min of 0.9 V is specified so that the customer can calculate how large a battery or capacitor they need for their

application. VDD min of 1.2 V or greater is needed to ensure speedy oscillator start-up time. For a restart condition, NXP recommends a

full '0 V' VDD value upon re-biasing.

[2]

Timer source clock = 1⁄60 Hz, level of pins SCL and SDA is VDD or VSS.

[3]

The I2C-bus interface of PCA85063A is 5 V tolerant.

[4]

Implicit by design.

[5]

Integrated load capacitance, CL(itg), is a calculation of COSCI and COSCO in series:

Oscillator

f

osc/fosc

relative oscillator

frequency variation

V

DD = 200 mV; Tamb =25 C

0.075

ppm

CL(itg)

integrated load

capacitance

on pins OSCO, OSCI

[5]

CL = 7 pF

4.2

9.8

CL = 12.5 pF

7.5

12.5

17.5

series resistance

100



Table 41.

Static characteristics …continued

VDD = 0.9 V to 5.5 V; VSS =0V; Tamb = 40 C to +105 C; fosc = 32.768 kHz; quartz Rs =60k; CL = 7 pF; unless otherwise

specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Litg



OSCI

OSCO





OSCI

OSCO



--------------------------------------------

Tamb =25 C; CLKOUT disabled.

(1) VDD =5.0 V.

(2) VDD =3.3 V.

Fig 23. Typical IDD with respect to fSCL

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