PCF8564A datasheet(6/59 Pages) NXP

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PCA85063A

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Product data sheet

Rev. 4 — 30 March 2018

6 of 59

NXP Semiconductors

PCA85063A

Automotive Real-Time Clock/calendar with alarm function and I2C-bus

8.2 Control registers

To ensure that all control registers will be set to their default values, the VDD level must be

at zero volts at initial power-up. If this is not possible, a reset must be initiated with the

software reset command when power is stable. Refer to Section 8.2.1.3 for details.

8.2.1 Register Control_1

[1]

Default value.

[2]

For a software reset, 01011000 (58h) must be sent to register Control_1 (see Section 8.2.1.3).

Table 6.

Control_1 - control and status register 1 (address 00h) bit description

Bit

Symbol

Value

Description

Reference

EXT_TEST

external clock test mode

Section 8.2.1.1

0[1]

normal mode

external clock test mode

unused

5STOP

STOP bit

Section 8.2.1.2

0[1]

RTC clock runs

RTC clock is stopped; all RTC divider chain

flip-flops are asynchronously set logic 0

4SR

software reset

Section 8.2.1.3

0[1]

no software reset

initiate software reset[2]; this bit always

returns a 0 when read

unused

2CIE

correction interrupt enable

Section 8.2.3

0[1]

no correction interrupt generated

interrupt pulses are generated at every

correction cycle

12_24

12 or 24-hour mode

Section 8.3.3

Section 8.5.3

0[1]

24-hour mode is selected

12-hour mode is selected

CAP_SEL

internal oscillator capacitor selection for

quartz crystals with a corresponding load

capacitance

0[1]

7 pF

12.5 pF

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