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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7LITE30 数据表(PDF) 116 Page - STMicroelectronics |
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ST7LITE30 数据表(HTML) 116 Page - STMicroelectronics |
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116 / 167 page  ST7LITE3 116/167 LINSCI ™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d) LIN PRESCALER FRACTION REGISTER (LPFR) Read/Write Reset Value: 0000 0000 (00h) Bits 7:4= Reserved. Bits 3:0 = LPFR[3:0] Fraction of LDIV These 4 bits define the fraction of the LIN Divider (LDIV): 1. When initializing LDIV, the LPFR register must be written first. Then, the write to the LPR register will effectively update LDIV and so the clock gen- eration. 2. In LIN Slave mode, if the LPR[7:0] register is equal to 00h, the transceiver and receiver input clocks are switched off. Examples of LDIV coding: Example 1: LPR = 27d and LPFR = 12d This leads to: Mantissa (LDIV) = 27d Fraction (LDIV) = 12/16 = 0.75d Therefore LDIV = 27.75d Example 2: LDIV = 25.62d This leads to: LPFR = rounded(16*0.62d) = rounded(9.92d) = 10d = Ah LPR = mantissa (25.620d) = 25d = 1Bh Example 3: LDIV = 25.99d This leads to: LPFR = rounded(16*0.99d) = rounded(15.84d) = 16d 7 0 0 0 0 0 LPFR 3 LPFR 2 LPFR 1 LPFR 0 LPFR[3:0] Fraction (LDIV) 0h 0 1h 1/16 ... ... Eh 14/16 Fh 15/16 |
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