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MWCT1014SFVLLPR 数据表(PDF) 14 Page - NXP Semiconductors

部件名 MWCT1014SFVLLPR
功能描述  Memory and memory interfaces
PDF  65 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

MWCT1014SFVLLPR 数据表(HTML) 14 Page - NXP Semiconductors

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• BUS_CLK = 48 MHz
• FLASH_CLK = 24 MHz
• VLPS Mode: All clock sources disabled.
Table 6. Power mode transition operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
tPOR
After a POR event, amount of time from the point VDD
reaches 2.7 V to execution of the first instruction
across the operating temperature range of the chip.
—
325
—
μs
VLPS → RUN
8
—
17
μs
STOP1 → RUN
0.07
0.075
0.08
μs
STOP2 → RUN
0.07
0.075
0.08
μs
VLPR → RUN
19
—
26
μs
VLPR → VLPS
5.1
5.7
6.5
μs
VLPS → VLPR
18.8
23
27.75
μs
RUN → Compute operation
0.72
0.75
0.77
μs
HSRUN → Compute operation
0.3
0.31
0.35
μs
RUN → STOP1
0.35
0.38
0.4
μs
RUN → STOP2
0.2
0.23
0.25
μs
RUN → VLPS
0.3
0.35
0.4
μs
RUN → VLPR
3.5
3.8
5
μs
VLPS → Asynchronous DMA Wakeup
105
110
125
μs
STOP1 → Asynchronous DMA Wakeup
1
1.1
1.3
μs
STOP2 → Asynchronous DMA Wakeup
1
1.1
1.3
μs
Pin reset → Code execution
—
214
—
μs
NOTE
HSRUN should only be used when frequencies in excess of 80
MHz are required. When using 80 MHz and below, RUN mode
is the recommended operating mode.
4.7 Power consumption
The following table shows the power consumption targets for the device in various
modes of operation. Attached MWCT101xS_Power_Modes _Configuration.xlsx details
the modes used in gathering the power consumption data stated in the following table
Table 7. For full functionality refer to table: Module operation in available low power
modes of the Reference Manual.
General
MWCT101XS Data Sheet, Rev. 3, 12/2019
14
NXP Semiconductors



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