LTC4230IGN datasheet(17/36 Pages) LINER

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LTC4230

4230f

reduces, and the internal servo loop disengages. At the

end of the soft-start cycle (Time Point 8), all RESET

n are

high and all SLOW COMP

n are armed.

Power-Off Cycle

As shown at Time Point 9, an external hard reset is initiated

by pulling the ON pin low (VON < 1.234V). All GATEn pin

voltages are ramped to ground by the internal 200

µA

current sources, discharging CGATEn and turning off the

pass transistors. As CLOADn discharges, the output voltage

crosses FBCOMP

n’s threshold, signaling a “power bad”

condition at Time Point 10. RESET

n then asserts low.

FIRST TIMING CYCLE

µA PULL-UP

LOAD CURRENT IS REGULATING AT 50mV/RSENSEn

4230 F06

NORMAL MODE

SECOND TIMING

CYCLE

CHECK FOR FILTER LOW (< VREF)

CHECK FOR FAULT HIGH (> VREF + 50mV)

CHECK FOR GATE

n < 0.25V

FAST COMPARATOR

ARMED

IF ON IS LOW AND

VFBn < 1.234V,

RESET 1, RESET 2 and RESET 3

PULL LOW, RESPECTIVELY

TIMER

GATE

VOUTn

ILOADn

GATE

VOUTn

RESET 1

RESET 2,

RESET 3

µA PULL-UP

200

µA PULL-DOWN

SLOW COMPARATOR ARMED

POWER GOOD

(VFBn > 1.237V)

POWER BAD

(VFBn < 1.234V)

200

µA PULL-DOWN

Figure 6. Normal Power-Up Sequence (with Current Limiting in Second Timing Cycle)

FREQUENCY COMPENSATION AT SOFT-START

If the external gate input capacitance (CISS) is greater than

600pF, no external gate capacitor is required at GATE

n to

stabilize the internal current-limiting loop during soft-

start. Otherwise, connect an external gate capacitor be-

tween the GATE

n and GND pins to increase the total gate

capacitance above 600pF. The servo loop that controls the

external MOSFET during current limiting has a unity-gain

frequency of about 105kHz and phase margin of 80

° for

external MOSFET gate input capacitances to 2.5nF.

APPLICATIO S I FOR ATIO

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