LTC4230IGN datasheet(24/36 Pages) LINER

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LTC4230

4230f

maximum rating for VGS is typically ±20V for standard

MOSFETs. However, the VGS maximum rating for logic-

level MOSFETs ranges from

±8V to ±20V depending upon

the manufacturer and the specific part number. The

LTC4230’s gate overdrive as a function of VCC is illustrated

in the Typical Performance curves. Logic-level MOSFETs

are recommended for low supply voltage applications and

standard MOSFETs can be used for applications where

supply voltage is greater than 4.75V.

Note that in some applications, the gate of the external

MOSFET can discharge faster than the output voltage

when the circuit breaker is tripped. This causes a negative

VGS voltage on the external MOSFET. Usually, the selected

external MOSFET should have a

±VGS(MAX) rating that is

higher than the operating input supply voltage to ensure

that the external MOSFET is not destroyed by a negative

VGS voltage. In addition, the ±VGS(MAX) rating of the

MOSFET must be higher than the gate overdrive voltage.

Lower

±VGS(MAX) rating MOSFETs can be used with the

LTC4230 if the GATE

n overdrive is clamped to a lower

voltage. The circuit in Figure 13 illustrates the use of zener

diodes to clamp the LTC4230’s GATE

n overdrive signal if

lower voltage MOSFETs are used.

The RDS(ON) of the external pass transistor should be low

to make its drain-source voltage (VDS) a small percentage

of VCC. At a VCC = 2.5V, VDS + VRSENSE = 0.1V yields 4%

error at the output voltage. This restricts the choice of

MOSFETs to very low RDS(ON). At higher VCC voltages, the

VDS requirement can be relaxed in which case MOSFET

package dissipation (PD and TJ) may limit the value of

RDS(ON). Table 5 lists some power MOSFETs that can be

used with the LTC4230.

Power MOSFET junction temperature is dependent on four

parameters: current delivered to the load, ILOAD, RDS(ON),

junction-to-ambient thermal resistance,

θJA,andthemaxi-

mum ambient temperature to which the circuit will be

exposed, TA(MAX). For reliable circuit operation, the maxi-

mum junction temperature (TJ(MAX)) for a power MOSFET

should not exceed the manufacturer’s recommended value.

This includes normal mode operation, start-up, current-

limit and autoretry mode in a fault condition. For a given

set of conditions, the junction temperature of a power

MOSFET is given by Equation 13:

MOSFET Junction Temperature,

TJ(MAX) ≤ (TA(MAX) + θJA • PD)

(13)

where

PD = (ILOAD)2 • RDS(ON)

PCB layout techniques for optimal thermal management

of power MOSFET power dissipation help to keep device

θJA as low as possible. See the section on PCB Layout

Considerations for more information.

VCC

VOUT

*USER SELECTED VOLTAGE CLAMP

(A LOW BIAS CURRENT ZENER DIODE IS RECOMMENDED)

1N4688 (5V)

1N4692 (7V): LOGIC-LEVEL MOSFET

1N4695 (9V)

1N4702 (15V): STANDARD-LEVEL MOSFET

4230 F13

RSENSE

200

Ω

GATE

D1*

D2*

Figure 13. Optional Gate Clamp for Lower VGS(MAX) MOSFETs

USING STAGGERED PIN CONNECTORS

The LTC4230 can be used on either a printed circuit board

or on the backplane side of the connector, and examples

for both are shown in Figure 14. Printed circuit board edge

connectors with staggered pins are recommended as the

insertion and removal of circuit boards do sequence the

pin connections. Supply voltage and ground connections

on the printed circuit board should be wired to the edge

connector’s long pins or blades. Control and status sig-

nals (like RESET

n, FAULT and ON) passing through the

card’s edge connector should be wired to short length pins

or blades.

APPLICATIO S I FOR ATIO

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