In a step-down converter, the input loop (including the input capacitor, the DC-DC regulator and ground

connection) is the most critical one due to high value pulsed currents flowing through it. In order to minimize the

EMI, this loop must be as short as possible with an adequate input capacitor placed very close to L7983 VIN and

GND (pin 8 and 10 respectively).

The feedback pin (FB) connection to the external resistor divider is a high impedance node, so the interference

can be minimized by placing the routing of the feedback node as far as possible from the high current paths. To

reduce the pick-up noise, the resistor divider must be placed very close to the device.

Thanks to the exposed pad of the device, the ground plane helps to reduce the junction to ambient thermal

resistance, so a wide ground plane enhances the thermal performance of the converter, allowing the high-power

conversion.

Refer to Section 6 Evaluation board for an example of the PCB layout.

5.7.5

Thermal considerations

The thermal design prevents the thermal shutdown of the device if junction temperature goes above 165 °C (typ.).

The three different sources of losses within the device are:

•

Conduction losses due to the non-negligible RDS(on) of the integrated power switches; these are equal to

PCOND=RHS,ON∙D∙IOUT2+RLS,ON∙ 1−D ∙IOUT2

(12)

of the power switches. Note that the duty cycle is theoretically given by the ratio between VOUT and VIN but

actually it is higher in order to compensate the losses of the regulator, so the conduction losses increase

compared with the ideal case;

•

Switching losses due to power MOSFETs turn-ON and OFF; these can be calculated as:

PSW=VIN∙IOUT∙ TRISE+TFALL

2 ∙FSW=VIN∙IOUT∙TTR∙FSW

(13)

the typical value for the equivalent switching time is 10 ns.

•

Quiescent current losses, calculated as follows:

PQ=VIN∙IQVIN+VBIAS∙IQVBIAS

(14)

PQVBIAS=VOUT=VIN∙ IQVIN,VBIAS=3.3V+  1ηL7983∙VBIASVIN

∙IQVBIAS, VBIAS=3.3V

(15)

If the switch-over feature is not used the total quiescent current losses are represented by:

PQVBIAS=GND=VIN∙IQVIN,VBIAS=GND

(16)

The L7983 total power losses are given by:

PLOSS=PCOND+PSW+PQ

(17)

TJ=TA+PLOSS∙RTH,JA

(18)

device; it can be calculated as the parallel of many paths of heat conduction from the junctions to the ambient. For

measured on the demonstration board described in the following section is about 50 °C/W.

L7983

Application design guidelines

DS13354 - Rev 1

page 25/43