ADRF5300

Data Sheet

Rev. 0 | Page 8 of 11

THEORY OF OPERATION

The ADRF5300 incorporates a driver to perform logic functions

internally and to provide the user with the advantage of a

simplified positive voltage control interface. The driver features

a single digital control input pin (CTRL) that controls the state

of the RF paths. The logic level applied to the CTRL pin

determines which RF port is in the insertion loss state and

which port is in the isolation state (see Table 7).

RF INPUT AND OUTPUT

All of the RF ports (RFC, RF1, and RF2) are dc-coupled to 0 V.

When the RF line potential is equal to 0 V, no dc blocking

capacitor is required at the RF ports.

The RF ports are internally matched to 50 Ω. Therefore,

external matching networks are not required.

The ADRF5300 is bidirectional with equal power handling

RFC port, RF1 port, or RF2 port.

The insertion loss path conducts the RF signal between the

selected RF throw port and the RF common port. The isolation

path provides high loss between the insertion loss path and the

unselected, reflective RF throw port.

POWER SUPPLY

The ADRF5300 operates on a positive single supply and

includes an NVG with ultralow spurious performance.

Bypassing capacitors are recommended on the supply lines to

filter high frequency noise.

The power-up sequence is as follows:

1. Connect GND to ground.

2. Power up the supply input, VDD.

3. Apply the digital control input, CTRL. Applying CTRL

before applying the VDD supply inadvertently forward

biases and damages the internal ESD protection structures.

To avoid this damage, use a series 1 kΩ resistor to limit the

current flowing into the CTRL pin. Pull the CTRL pin to

VDD or GND using a resistor if the controller output is in

a high impedance state after VDD is powered up and the

CTRL pin is not driven to a valid logic state.

4. Apply the RF input signal.

The power-down sequence is the reverse order of the power-up

sequence.

TIMING REQUIREMENTS

There are timing requirements for the proper operation of the

bias and control circuits. See Table 2 for the timing specifications.

See Figure 14 for the timing requirements.

time before the recommended maximum RF power can be applied.

During this time, a maximum of 10 dBm RF input power can

be applied.

The maximum rise and fall time of the CTRL pulse is defined

VDD

VDD

GND

HIGH

LOW

CTRL

RFC

RF1

RF2

Figure 14. Timing Requirements

Table 7. Control Voltage Truth Table

Digital Control Input

RF Paths

CTRL

RF1 to RFC

RF2 to RFC

High

Insertion loss (on)

Isolation (off)

Low

Isolation (off)

Insertion loss (on)