ADL5920ACPZ-R2 datasheet(25/26 Pages) AD

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Data Sheet

ADL5920

Rev. B | Page 25 of 26

Component

Function Description/Comments

Default Value

VNEG, C5, C15, R3, R8, C10

Negative supply. The main signal path from RFIN and RFOUT

can be dc-coupled by connecting a −2.5 V supply to the VNEG

test loop and replacing ac coupling capacitors, C2 and C19,

with 0 Ω resistors. R3 and R8 must be removed and replaced

with 100 pF capacitors pins. Connect the DECL pin to ground

by removing C10 and replacing it with a 0 Ω resistor. In this

mode, the voltage on VPOS must remain at 5 V.

VNEG = 0 V,

R3 = R8 = 0 Ω (0603),

C15 = C5 = 0.1 µF (0402),

C10 = 4.7 µF (0402)

R6, R7

VTGT interface. R7 and R6 are driven from VREF (2.5 V) and

provide 1 V to VTGT. If R6 and R7 are removed, an external

voltage can be applied on the VTGT test point.

R7 = 2.43 kΩ, R6 = 3.6 kΩ,

VTGT = 1 V

C7, C13

RMS detector offset compensation loop. The capacitances on

these pins set the corner frequency of internal offset

compensation loops of the two rms detectors. These loops

limit the minimum input frequency that can be sensed by the

ADL5920. The default values for these capacitors set minimum

input frequencies that are well below the frequency corner set

by the ac-coupling capacitors in the main signal path. These

capacitors are deliberately located as close as possible to Pin 3

and Pin 4 and Pin 21 and Pin 22. To achieve the specified

directivity when operating above 2 GHz, remove these

capacitors (see Figure 5).

C7, C13 = 0.1 µF (0201)

S1, R1, R2, PWDN/TADJS

Device enable and slope temperature compensation. S1 is

used to disable the ADL5920 by connecting the PWDN/TADJS

pin to VPOS. In its other position, S1 is open and the voltage

on PWDN/TADJS is set by VREF (2.5 V) and the R1, R2 resistor

divider. This voltage is used to fine tune the temperature

stability of the slope of the rms detectors.

S1 = open position,

R1 = 0 Ω DNI,

R2 = 100 Ω,

PWDN/TADJS = 0 V

VTEMP

Temperature sensor output. This yellow test loop is connected

directly to Pin 6 of the ADL5920 (VTEMP).

Not applicable

VRMSF, RMSR, VRMS_F, RMS_R

Reverse and forward rms voltage measurement. The voltages

on these connectors are proportional to the dB power of the

forward and reverse signals in the bridge circuit.

VRMSF, VRMSR = SMA

end launch connector,

VRMS_F, VRMS_R =

yellow test loops

C8, C12

RMS averaging capacitors. The value of the rms averaging

capacitor must be set based on the peak to average ratio of

the input signal and based on the desired output response

time and residual output noise on the rms detector outputs.

C8 = C12 = 0.1 µF (0402)

VOCM, R4, R5

Common-mode voltage for VDIFF+ and VDIFF−. The voltage

on VOCM pin (Pin 10) sets the common-mode level for the

VDIFF+ and VDIFF− differential pair. The nominal voltage on

this pin must be 2.5 V. This input requires a bias current of

±1 mA and must be driven from a low impedance source. The

nominal biasing method for VOCM is to connect it to VREF and

connecting a 1 kΩ resistor from VOCM to ground. An external

voltage can be applied VOCM through Pin 8 of the P1 connector.

R4 = 0 Ω (0402),

R5 = 1 kΩ (0402),

VOCM = 2.5 V

VDIFF+, VDIFF−, VDIFFN, VDIFFP

Return loss measurement. The output voltage from this

differential pair is proportion to the ratio of the forward and

reverse power in the bridge circuit. The common-mode level is

set by the voltage on VOCM.

VDIFF+, VDIFF− = SMA

end launch connector,

VDIFFN, VDIFFP = yellow

test loops

R9, R10, TADJI

TADJI interface. R9 and R10 set the voltage on the TADJI pin

that is derived from VREF. This voltage is used to fine tune the

temperature stability of the Intercept of the rms detectors.

R9 = 0 Ω DNI,

R10 = 100 Ω (0402),

TADJI = 0 V

P1 header. The P1 header can access all of the dc levels on the

evaluation board.

Not applicable

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