Data Sheet

ADL5920

Rev. B | Page 9 of 26

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

24 GND2

23 VNEG2

22 CHPF–

21 CHPF+

20 TADJI

19 VREF

18 VRMSF

17 VPOS3

1

2

3

4

5

6

7

8

GND1

VNEG1

CHPR+

CHPR–

PWDN/TADJS

VTEMP

VRMSR

VPOS1

ADL5920

TOP VIEW

(Not to Scale)

NOTES

1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A GROUND PLANE

WITH LOW THERMAL AND ELECTRICAL IMPEDANCE.

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 24, 27 to 30

GND1, GND2, GND3,

GND4, GND5, GND6

RF Ground. Connect all ground pins to a low impedance ground plane.

2, 23

VNEG1, VNEG2

Negative Supply Pins. For normal single-supply operation, connect these pins to ground.

In applications where the RF input and output are dc-coupled, apply a −2.5 V supply

voltage to these pins along with a +5 V power supply on VPOS1, VPOS2, and VPOS3.

In this dc-coupled operating mode, Pin 12 (DECL) must be connected to ground.

8, 13, 17

VPOS1, VPOS2, VPOS3

Power Supply. Separately decouple each power supply pin using 100 pF and 0.1 µF

capacitors. The nominal supply voltage on these pins is 5 V.

3, 4, 21, 22

CHPR+, CHPR−, CHPF+, CHPF−

Offset Compensation Loop Control. The capacitances on these pin pairs set the high-

pass corner frequency of the internal offset compensation loops, which in turn sets the

minimum operating frequency of the rms detectors in the forward and reverse paths.

For normal operation, add a capacitor from each pin to ground along with a capacitor

across the pins. To operate at input frequencies down to 9 kHz, capacitances in the 1 µF

range are required. To maintain the specified directivity, leave these pins open when

operating at frequencies above 2 GHz.

5

PWDN/TADJS

Temperature Compensation and Shutdown. This pin is a dual function pin that controls

temperature slope compensation at voltages <1.0 V and/or shuts down the device at

voltages >1.4 V. The temperature compensation voltage is set by connecting this pin to

VREF through a resistor divider.

6

VTEMP

7, 18

VRMSR, VRMSF

Reverse and Forward RMS Voltage Measurement. The voltages on these pins are

proportional to the decibel power of the incident signal to the RFOUT and RFIN pins.

9, 16

CRMSR, CRMSF

RMS Averaging Capacitor for Reverse and Forward Path Detectors. Connect rms

averaging capacitors between CRMSR and ground and between CRMSF and ground to

set the averaging time constant of the forward and reverse rms detectors. For normal

operation, the values of these two capacitors must be equal.

10

VOCM

Common-Mode Input Voltage for VDIFF+ and VDIFF−. The input voltage applied to

VOCM sets the common-mode voltage for the VDIFF+ and VDIFF− differential pair.

The nominal voltage on this pin is 2.5 V. However, this value can be reduced to as low as

1.5 V to accommodate the common-mode requirements of the ADC, which is driven by

VDIFF+ and VDIFF−. The VOCM input requires a bias current of ±1 mA and must be

driven from a low impedance source. VOCM can be driven from the VREF pin but the

connection must include a 1 kΩ resistor to ground.

11, 14

VDIFF−, VDIFF+

Return Loss and VSWR Output. The differential voltage on these pins is proportional to

the dB return loss of the load connected to the RFOUT port when the device is driven

through the RFIN port. This differential voltage has a bias level equal to the voltage

applied to VOCM, nominally 2.5 V.