Philips Semiconductors

Preliminary specification

80C453/83C453/87C453

CMOS single-chip 8-bit microcontrollers

1996 Aug 15

3-321

ODS is active low for output driver control. The OBF flag can be

programmed to be cleared on the negative or positive edge of ODS.

Can produce an IOB interrupt (see Figure 2).

IDS – Input data strobe for port 6. IDS is used to control the port 6

input latch and input buffer full flag (IBF) bit in the CSR. The input

data latch can be programmed to be transparent when IDS is low

and latched on the positive transition of IDS, or to latch only on the

positive transition of IDS. Correspondingly, the IBF flag is set on the

negative or positive transition of IDS. Can produce an IIB interrupt

(see Figure 2).

AFLAG – AFLAG is a bidirectional I/O pin which can be

programmed to be an output set high or low under program control,

or to output the state of the output buffer full flag. AFLAG can also

be programmed to be an input which selects whether the contents of

the output buffer, or the contents of the port 6 control status register

will output on port 6. This feature grants complete port 6 status to

external devices.

BFLAG – BFLAG is a bidirectional I/O pin which can be

programmed to be an output, set high or low under program control,

or to output the state of the input buffer full flag. BFLAG can also be

programmed to input an enable signal for port 6. When BFLAG is

used as an enable input, port 6 output drivers are in the

high-impedance state, and the input latch does not respond to the

IDS strobe when BFLAG is high. Both features are enabled when

BFLAG is low. This feature facilitates the use of the 87C453 in

bused multiprocessor systems.

CONTROL STATUS REGISTER

The control status register (CSR) establishes the mode of operation

for port 6 and indicates the current status of port 6 I/O registers. All

control status register bits can be read and written by the CPU,

except bits 0 and 1, which are read only. Reset writes ones to bits 2

through 7, and writes zeros to bits 0 and 1 (see Table 3).

CSR.0 Input Buffer Full Flag (IBF) (Read Only) – The IBF bit is

set to a logic 1 when port 6 data is loaded into the input buffer under

control of IDS. This can occur on the negative or positive edge of

IDS, as determined by CSR.2. When IBF is set, the Interrupt Enable

Register bit IIB (IE.5) is set. The Interrupt Service Routine vector

address for this interrupt is 002BH. IBF is cleared when the CPU

reads the input buffer register.

CSR.1 Output Buffer Full Flag (OBF) (Read Only) – The OBF flag

is set to a logic 1 when the CPU writes to the port 6 output data

buffer. OBF is cleared by the positive or negative edge of ODS, as

determined by CSR.3. When OBF is cleared, the Interrupt Enable

Register bit IOB (IE.6) is set. The Interrupt Service Routine vector

address for this interrupt is 0033H.

CSR.2 IDS Mode Select (IDSM) – When CSR.2 = 0, a low-to-high

transition on the IDS pin sets the IBF flag. The Port 6 input buffer is

loaded on the IDS positive edge. When CSR.2 = 1, a high-to-low

transition on the IDS pin sets the IBF flag. Port 6 input buffer is

transparent when IDS is low, and latched when IDS is high.

CSR.3 Output Buffer Full Flag Clear Mode (OBFC) – When

CSR.3 = 1, the positive edge of the ODS input clears the OBF flag.

When CSR.3 = 0, the negative edge of the ODS input clears the

OBF flag.

CSR.4, CSR.5 AFLAG Mode Select (MA0, MA1) – Bits 4 and 5

select the mode of operation for the AFLAG pin as follows:

MA1

MA0

AFLAG Function

0

0

Logic 0 output

0

1

Logic 1 output

1

0

OBF flag output (CSR.1)

1

1

Select (SEL) input mode

The select (SEL) input mode is used to determine whether the port 6

data register or the control status register is output on port 6. When

the select feature is enabled, the AFLAG input controls the source of

port 6 output data. A logic 0 on AFLAG input selects the port 6 data

register, and a logic 1 on AFLAG input selects the control status

register.

The value of the AFLAG input is latched into the Auxiliary Register

(AUXR) bit 1 (AUXR.1). Checking this bit (AF) will allow the

87C453’s program to determine if Port 6 was loaded with data or a

UPI command.

CSR.6, CSR.7 BFLAG Mode Select (MB0, MB1) – Bits 6 and 7

select the mode operation as follows:

MB1 MB0

BFLAG Function

0

0

Logic 0 output

0

1

Logic 1 output

1

0

IBF flag output (CSR.0)

1

1

Port enable (PE)

In the port enable mode, IDS and ODS inputs are disabled when

BFLAG input is high. When the BFLAG input is low, the port is

enabled for I/O.

Reduced EMI Mode – The on–chip clock distribution drivers have

been identified as the cause of most of the EMI emissions from the

80C51 family. By tailoring the clock drivers properly, a compromise

between maximum operating speed and minimal EMI emissions can

be achieved. Typically, an order in magnitude of reduction is

possible over previous designs. This feature has been implemented

on this chip along with the additional capability of turning off the ALE

output. Setting the AO bit (AUXR.0) in the AUXR special function

register will disable the ALE output. Reset forces a 0 into AUXR.0 to

enable normal 80C51 type operation.

Auxiliary Register (AUXR)

76

54

32

10

–

–

–

–

–

–

AF

AO

Latched value of AFLAG when Port 6

inputs data from IDS strobe

0 = ALE enabled

1 = ALE disabled