 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
P83C453EBAA 数据表(PDF) 14 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
P83C453EBAA 数据表(HTML) 14 Page - NXP Semiconductors |
|
|
14 / 23 page  Philips Semiconductors Preliminary specification 80C453/83C453/87C453 CMOS single-chip 8-bit microcontrollers 1996 Aug 15 3-324 AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V 16MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL Oscillator frequency 3.5 16 MHz tLHLL 9 ALE pulse width 85 2tCLCL–40 ns tAVLL 9 Address valid to ALE low 22 tCLCL–40 ns tLLAX 9 Address hold after ALE low 32 tCLCL–30 ns tLLIV 9 ALE low to valid instruction in 150 4tCLCL–100 ns tLLPL 9 ALE low to PSEN low 32 tCLCL–30 ns tPLPH 9 PSEN pulse width 142 3tCLCL–45 ns tPLIV 9 PSEN low to valid instruction in 82 3tCLCL–105 ns tPXIX 9 Input instruction hold after PSEN 0 0 ns tPXIZ 9 Input instruction float after PSEN 37 tCLCL–25 ns tAVIV 9 Address to valid instruction in 207 5tCLCL–105 ns tPLAZ 9 PSEN low to address float 10 10 ns Data Memory tRLRH 10, 11 RD pulse width 275 6tCLCL–100 ns tWLWH 10, 11 WR pulse width 275 6tCLCL–100 ns tRLDV 10, 11 RD low to valid data in 147 5tCLCL–165 ns tRHDX 10, 11 Data hold after RD 0 0 ns tRHDZ 10, 11 Data float after RD 65 2tCLCL–60 ns tLLDV 10, 11 ALE low to valid data in 350 8tCLCL–150 ns tAVDV 10, 11 Address to valid data in 397 9tCLCL–165 ns tLLWL 10, 11 ALE low to RD or WR low 137 239 3tCLCL–50 3tCLCL+50 ns tAVWL 10, 11 Address valid to WR low or RD low 122 4tCLCL–130 ns tQVWX 10, 11 Data valid to WR transition 13 tCLCL–50 ns tWHQX 10, 11 Data hold after WR 13 tCLCL–50 ns tRLAZ 10, 11 RD low to address float 0 0 ns tWHLH 10, 11 RD or WR high to ALE high 23 103 tCLCL–40 tCLCL+40 ns Shift Register tXLXL 12 Serial port clock cycle time 750 12tCLCL ns tQVXH 12 Output data setup to clock rising edge 492 10tCLCL–133 ns tXHQX 12 Output data hold after clock rising edge 8 2tCLCL–117 ns tXHDX 12 Input data hold after clock rising edge 0 0 ns tXHDV 12 Clock rising edge to input data valid 492 10tCLCL–133 ns Port 6 input (input rise and fall times = 5ns) tFLFH 15 PE width 209 3tCLCL+20 ns tILIH 15 IDS width 209 3tCLCL+20 ns tDVIH 15 Data setup to IDS high or PE high 0 0 ns tIHDZ 15 Data hold after IDS high or PE high 30 30 ns tIVFV 16 IDS to BFLAG (IBF) delay 130 130 ns |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
