Block Diagram

Pin Assignment

HT83XXX

Rev. 0.10

2

August 25, 2003

Preliminary

P r o g r a m

C o u n t e r

P r o g r a m

R O M

I n s t r u c t i o n

R e g i s t e r

I n s t r u c t i o n

D e c o d e r

T i m i n g

G e n e r a t i o n

O S C 1

R E S

V D D

V S S

I n t e r r u p t

C i r c u i t

I N T C

M P 0

M

U

X

M U X

D A T A

M e m o r y

A L U

S h i f t e r

S T A T U S

A C C

T M R 0

T M R 0 C

S Y S C L K

8 - b i t

L V D / L V R

P A C

P A

P O R T A

P A 0 ~ P A 7

S T A C K 2

S T A C K 3

S T A C K 0

S T A C K 1

S Y S C L K / 4

H A L T

E N / D I S

T i m e B a s e

S Y S C L K / 1 0 2 4

W D T S

W D T P r e s c a l e r

¸ 2 5 6

W D T R C

O S C

M

U

X

S Y S C L K / 4

P W M

S Y S C L K

P W M 1

P W M 2

8 - s t a g e P r e s c a l e r

T M R 1

T M R 1 C

S Y S C L K

8 - b i t

8 - s t a g e P r e s c a l e r

1

2

3

4

5

6

7

8

9

1 0

1 1

1 2

1 3

1 4

1 5

1 6

H T 8 3 0 0 3 / H T 8 3 0 0 6 / H T 8 3 0 0 9 / H T 8 3 0 1 8

H T 8 3 0 3 6 / H T 8 3 0 4 8 / H T 8 3 0 7 2

3 2 D I P - A

3 2

3 1

3 0

2 9

2 8

2 7

2 6

2 5

2 4

2 3

2 2

2 1

2 0

1 9

1 8

1 7

N C

N C

N C

N C

N C

N C

P W M 2

P W M 1

V D D A

V D D

V S S A

V S S

O S C 1

R E S

P A 7

P A 6

N C

N C

N C

N C

N C

N C

N C

N C

N C

N C

P A 0

P A 1

P A 2

P A 3

P A 4

P A 5