FUSB3307

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17

Table 9. PDIV2 Pin Changing Advertised PD Power

PDIV2 Pin State

Advertised PDP (Power Delivery Power)

1

100% of TrimPDP

0

50% of TrimPDP

With the SOIC package and PDIV0 and PDIV1 pins

selected, the power can be controlled as shown below. In this

case there is no PDIV2 pin and the PDIV0 and PDIV1 pins

are used to trim power, as shown in Table 10.

Table 10. PDIV0 and PDIV1 Pins Changing Advertised

PD Power

PDIV1 Pin State PDIV0 Pin State

Advertised PDP

(Power Delivery Power)

1

1

100% of TrimPDP

1

1

75% of TrimPDP

0

1

50% of TrimPDP

0

0

25% of TrimPDP

If PDIV2 is also available (i.e. QFN package) and in the

above trim table (Table 6) the pins D+/PDIV1 and

D−/PDIV0 allow PDIV0 and PDIV1 to be available as pins,

then this is the PDP advertised, as shown in Table 11.

Table 11. PDIV0, PDIV1 and PDIV2 Pins Changing

Advertised PD Power

PDIV2

Pin State

PDIV1

Pin State

PDIV0

Pin State

Advertised PDP (Pow-

er Delivery Power)

1

1

1

100% of TrimPDP

1

1

0

87.5% of TrimPDP

1

0

1

75% of TrimPDP

1

0

0

62.5% of TrimPDP

0

1

1

50% of TrimPDP

0

1

0

37.5% of TrimPDP

0

0

1

25% of TrimPDP

0

0

0

12.5% of TrimPDP

In all the above calculations, no Advertised PDP will ever

go below 16 W minimum if in a USB PD contract. For

example, if TrimPDP=100 and when PDIV0, PDIV1 and

PDIV2

pins

are

available

and

they

are

[PDIV2:PDIV1:PDIV0] = 001 then Advertised PDP is

25 W (100W*25%). However if TrimPDP=60, then

Advertised PDP is 16 W not 15 W (60W*25%).

When any of these pins, PDIV0, PDIV1 and PDIV2 are

changed, the connected PD Sink has to ask for Source

Capabilities to get these new capabilities or if this Sink or the

FUSB3307 executes a Soft_Reset or Hard Reset which causes

the new advertised capabilities to be sent by the FUSB3307.

Alternatively recovery from any protection operation would

cause the FUSB3307 to advertise the new PDP values based

on the PDIV0, PDIV1 and PDIV2 pins setting.

Protection Operation

FUSB3307 has a number of ways it protects itself as

shown in Table 12.

Table 12. Protection Modes Available

Symbol

Description

Pin(s) Used

Package

OVP

Output Voltage Over Voltage Protection

VCC

SOIC & QFN

UVP

Output Voltage Under Voltage Protection

VCC

SOIC & QFN

OCP

Over Current Protection

IS+ & IS−

SOIC & QFN

I_OTP

Internal Over Temperature Protection

none

SOIC & QFN

E_OTP

External Over Temperature Protection

NTC

QFN only

CC_OVP

CC1 or CC2 Over Voltage Protection

CC1 / CC2

SOIC & QFN

VCONN_OCP

CC1 or CC2 VCONN Over Current Protection

CC1 / CC2

SOIC & QFN