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TSV7721 数据表(PDF) 20 Page - STMicroelectronics |
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TSV7721 数据表(HTML) 20 Page - STMicroelectronics |
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20 / 40 page ![]() Figure 46. EMIRR on In+, In- and Out pins EMIRR performances might be improved by adding small capacitances (in the pF range) on the inputs, power supply and output pins. These capacitances help to minimize the impedance of these nodes at high frequencies. 5.5 Maximum power dissipation The usable output load current drive is limited by the maximum power dissipation allowed by the device package. The absolute maximum junction temperature for the TSV7722 is 150 °C. The junction temperature can be estimated as follows: TJ=PD×θJA+TA (3) TJ is the die junction temperature PD is the power dissipated in the package θJA is the junction to ambient thermal resistance of the package. TA is the ambient temperature. The power dissipated in the package PD is the sum of the quiescent power dissipated and the power dissipated by the output stage transistor. It is calculated as follows: PD= VCC×ICC + VCC+−VOUT ×ILoadwhentheopampissourcingthecurrent. PD= VCC×ICC + VOUT−VCC− ×ILoadwhentheopampissinkingthecurrent. Do not exceed the 150 °C maximum junction temperature for the device. Exceeding the junction temperature limit can cause degradation in the parametric performance or even destroy the device. 5.6 Capacitive load and stability Stability analysis must be performed for large capacitive loads over 47 pF; increasing the load capacitance to high values produces gain peaking in the frequency response, with overshoot and ringing in the step response. Generally, unity gain configuration is the worst situation for stability and the ability to drive large capacitive loads. For additional capacitive load drive capability in unity-gain configuration, stability can be improved by inserting a small resistor RISO (10 Ω to 22 Ω) in series with the output (see Figure 35. Small step overshoot vs. load capacitance). This resistor significantly reduces ringing while maintaining DC performance for purely capacitive loads. However, if there is a resistive load in parallel with the capacitive load, a voltage divider is created introducing a gain error at the output and slightly reducing the output swing. The error introduced is proportional to the ratio RISO / RL. RISO modifies the maximum capacitive load acceptable from a stability point of view, as described in Figure 47. Test configuration for RISO: TSV7721, TSV7722, TSV7723 Maximum power dissipation DS13614 - Rev 3 page 20/40 |
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