5.8

Settling time

Settling time in an application can be defined as the amount of time between the input changes, and the output

reaching its final value. It is usually defined with a given tolerance, so the output stability is reached when the

output stays within the given range around the final value. In Figure 33. Settling time output high to low at

VCC = 5 V and Figure 34. Settling time output low to high at VCC = 5 V, the settling time is measured in an

inverting configuration, using the so-called “false summing node” circuit.

This circuit is used with a step input voltage from a positive or negative value, to 0 V. The measurement point

settling time. This characteristic is particularly useful when driving an ADC. It is related to the slew rate, GBP and

stability of the circuit. It also varies with the circuit gain, the circuit load, and the input voltage step value. However,

computing the value of the settling time in a given configuration is not straightforward. The macromodel can give a

good estimation, but prototyping can be needed for fine circuit optimization.

TSV7721, TSV7722, TSV7723

Settling time

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