List of figures

Figure 1.

Pin connections (top view) ............................................................ 2

Figure 2.

Pin connections (top view) ............................................................ 3

Figure 3.

Pin connections (top view) ............................................................ 4

Figure 4.

Supply current vs. supply voltage ...................................................... 12

Figure 5.

Input offset voltage distribution at VCC = 5 V ............................................... 12

Figure 6.

Input offset voltage distribution at VCC = 1.8 V ............................................. 12

Figure 7.

Input offset voltage vs. temperature at VCC = 5 V ........................................... 12

Figure 8.

Input offset voltage vs. temperature at VCC=1.8 V ........................................... 12

Figure 9.

Input offset voltage thermal coeff. at VCC=5 V.............................................. 12

Figure 10.

Input offset voltage thermal coefficient at VCC=1.8 V ......................................... 13

Figure 11.

Input offset voltage vs. supply voltage ................................................... 13

Figure 12.

Input offset voltage vs. common-mode voltage at VCC = 5 V .................................... 13

Figure 13.

Input offset voltage vs. common-mode voltage at VCC = 1.8 V .................................. 13

Figure 14.

Input bias current vs. temp. at VICM = VCC / 2 .............................................. 13

Figure 15.

Input bias current vs. common-mode voltage at VCC = 5 V ..................................... 13

Figure 16.

Output current vs. output voltage at VCC = 5 V ............................................. 14

Figure 17.

Output current versus output voltage at VCC=1.8 V .......................................... 14

Figure 18.

Output saturation voltage (VOL) vs. supply voltage .......................................... 14

Figure 19.

Output saturation voltage (VOH) vs. supply voltage .......................................... 14

Figure 20.

Positive slew rate at VCC = 5 V ........................................................ 14

Figure 21.

Negative slew rate at VCC = 5 V ....................................................... 14

Figure 22.

Slew rate vs. VCC ................................................................. 15

Figure 23.

Open loop bode diagram at VCC = 5 V ................................................... 15

Figure 24.

Open loop bode diagram at VCC = 1.8 V ................................................. 15

Figure 25.

Closed loop bode diagram at VCC = 5 V.................................................. 15

Figure 26.

Closed loop bode diagram at VCC = 1.8 V ................................................ 15

Figure 27.

Phase margin vs. common-mode voltage and load current at VCC = 5 V ........................... 15

Figure 28.

Phase margin vs. capacitive load ...................................................... 16

Figure 29.

Small step response at VCC = 5 V ...................................................... 16

Figure 30.

Small step response at VCC = 1.8 V..................................................... 16

Figure 31.

Desaturation from low rail at VCC = 5 V .................................................. 16

Figure 32.

Desaturation from high rail at VCC = 5 V.................................................. 16

Figure 33.

Settling time output high to low at VCC = 5 V............................................... 16

Figure 34.

Settling time output low to high at VCC = 5 V............................................... 17

Figure 35.

Small step overshoot vs. load capacitance ................................................ 17

Figure 36.

Linearity vs. load resistance at VCC = 5 V................................................. 17

Figure 37.

Noise vs. frequency................................................................ 17

Figure 38.

Noise versus time at VCC = 5 V........................................................ 17

Figure 39.

THD+N vs. frequency .............................................................. 17

Figure 40.

THD+N vs. output voltage ........................................................... 18

Figure 41.

CMRR vs. frequency at VCC = 5 V...................................................... 18

Figure 42.

PSRR vs. frequency at VCC = 5 V ...................................................... 18

Figure 43.

Supply current vs. supply voltage in shutdown mode ......................................... 18

Figure 44.

Turn-on time at VCC = 5 V ........................................................... 18

Figure 45.

Turn-on time at VCC = 1.8 V .......................................................... 18

Figure 46.

EMIRR on In+, In- and Out pins ....................................................... 20

Figure 47.

Test configuration for RISO ........................................................... 21

Figure 48.

Inverting amplifier configuration with parasitic input capacitances ................................ 21

Figure 49.

Settling time measurement configuration ................................................. 22

TSV7721, TSV7722, TSV7723

List of figures

DS13614 - Rev 3

page 38/40