M28F420 datasheet(5/38 Pages) STMICROELECTRONICS

5 / 38 page

Mne-

monic

Bit

Name

Logic

Level

Definition

Note

P/ECS

P/E.C. Status

’1’

Ready

Indicates the P/E.C. status, check during Program

or Erase, and on completion before checking bits

b4 or b5 for Program or Erase Success

’0’

Busy

ESS

Erase

Suspend

Status

’1’

Suspended

On an Erase Suspend instruction P/ECS and

ESS bits are set to ’1’. ESS bit remains ’1’ until an

Erase Resume instruction is given.

’0’

In progress or

Completed

Erase Status

’1’

Erase Error

ES bit is set to ’1’ if P/E.C. has applied the

maximum number of erase pulses to the block

without achieving an erase verify.

’0’

Erase Success

Program

Status

’1’

Program Error

PS bit set to ’1’ if the P/E.C. has failed to program

a byte or word.

’0’

Program

Success

VPPS

VPP Status

’1’

VPP Low, Abort

VPPS bit is set if the VPP voltage is below

VPPH(min) when a Program or Erase instruction

has been executed.

’0’

VPP OK

Reserved

Notes: Logic level ’1’ is High, ’0’ is Low.

Table 7. Status Register

is first applied, on exit from power down or if VCC

falls below VLKO, the command interface is reset to

Read Memory Array.

Instructions and Commands

Eight Instructions are defined to perform Read

Memory Array, Read Status Register, Read Elec-

tronic Signature, Erase, Program, Clear Status

internal Program/EraseController (P/E.C.) handles

all timing and verification of the Program and Erase

instructions and provides status bits to indicate its

operation and exit status. Instructions are com-

posed of a first command write operation followed

by either second command write, to confirm the

commands for programming or erase, or a read

operation to read data from the array, the Electronic

Signature or the Status Register.

For added data protection, the instructions for byte

or word program and block erase consist of two

commands that are written to the memory and

which start the automatic P/E.C. operation. Byte or

word programming takes typically 9

μs, block erase

typically 1 second. Erasure of a memory block may

be suspended in order to read data from another

block and then resumed. A Status Register may be

read at any time, including during the programming

or erase cycles, to monitor the progress of the

operation.

Power Saving

The M28F410 and M28F420 have a number of

power saving features. A CMOS standby mode is

entered when the Chip Enable E and the Re-

set/Power Down (RP) signals are at VCC, when the

supply current drops to typically 60

μA. A deep

power down mode is enabled when the Re-

set/Power Down (RP) signal is at VSS, when the

supply current drops to typically 0.2

μA. The time

required to awake from the deep power down mode

is 300ns maximum, with instructions to the C.I.

recognised after only 210ns.

5/38

M28F410, M28F420

M28F420 数据表(PDF) 5 Page - STMicroelectronics

M28F420 数据表(HTML) 5 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

数据表下载