MCP47FVB01 datasheet(53/92 Pages) MICROCHIP

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DS20005429B-page 53

MCP48FEBXX

6.0

SPI SERIAL INTERFACE

MODULE

The MCP48FEBXX’s SPI Serial Interface Module

supports the SPI serial protocol specification.

Figure 6-1 shows a typical SPI interface connection.

The command format and waveforms for the

MCP48FEBXX is defined in Section 7.0 “SPI

Commands”

6.1

Overview

This sections discusses some of the specific

characteristics of the MCP48FEBXX’s Serial Interface

Module.

The following sections discuss some of these

device-specific characteristics:

• Communication Data Rates

• POR/BOR

• Interface Pins (CS, SCK, SDI, SDO, and

LAT/HVC)

6.2

SPI SERIAL INTERFACE

The MCP48FEBXX devices support the SPI serial

protocol. This SPI operates in slave mode (does not

generate the serial clock).

The SPI interface uses up to four pins. These are:

•CS - Chip Select

• SCK - Serial Clock

• SDI - Serial Data In

• SDO - Serial Data Out

An additional HVC pin is available for High Voltage

command support. High Voltage commands allow the

device to enable and disable nonvolatile configuration

bits. Without high voltage present, those bits are

inhibited from being modified.

Typical SPI Interfaces are shown in Figure 6-1. In the

SPI interface, the Master’s Output pin is connected to

the Slave’s Input pin, and the Master’s Input pin is

connected to the Slave’s Output pin.

The MCP48FEBXX SPI’s module supports two (of the

four) standard SPI modes. These are Mode 0,0 and

1,1

. The SPI mode is determined by the state of the

SCK pin (VIH or VIL) when the CS pin transitions from

inactive (VIH) to active (VIL).

The HVC pin is high-voltage tolerant. To enter a

high voltage command, the HVC pin must be greater

than the VIHH voltage.

6.3

Communication Data Rates

The MCP48FEBXX supports clock rates (bit rate) of up

to 20 MHz for write commands and 10 MHz for read

commands.

For most applications, the write time will be considered

more important, since that is how the device operation

is controlled.

6.4

POR/BOR

On a POR/BOR event, the SPI Serial Interface Module

state machine is reset, which includes that the

Device’s Memory Address pointer is forced to 00h.

FIGURE 6-1:

Typical SPI Interface Block Diagram.

SDI

SDO

MCP48FEBXX

SDO

SDI

SCK

(Master Out - Slave In (MOSI))

(Master In - Slave Out (MISO))

Host

Controller

Typical SPI Interface Connections

I/O

Note 1:

If High Voltage commands are desired, some type of external circuitry needs to be implemented.

Requires the VIHH voltage to enable the High Voltage commands.

HVC (2)

I/O (1)

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