MCP47FVB01 datasheet(62/92 Pages) MICROCHIP

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MCP48FEBXX

DS20005429B-page 62

 2015 Microchip Technology Inc.

7.2

Read Command

The Read command is a 24-bit command and is used

to transfer data from the specified memory location to

the Host controller. The Read command can be issued

to both the volatile and nonvolatile memory locations.

The format of the command as well as an example SDI

and SDO data is shown in Figure 7-7.

The first 7-bits of the Read command determine the

address and the command. The 8th clock will output

the CMDERR bit on the SDO pin. By means of the

remaining 16 clocks, the device will transmit the data

bits of the specified address (AD4:AD0).

During an EEPROM write cycle (write to nonvolatile

memory

location

Enable/Disable

Configuration

Bit

command), the Read

command can only read the volatile memory locations.

By reading the Status Register (0Ah), the Host

Controller can determine when the write cycle has

completed (via the state of the EEWA bit)

The Read command formats include:

• Single Read

• Continuous Reads

7.2.1

LAT PIN INTERACTION

During a Read command of the DACx Registers, if the

LAT pin transitions from VIH to VIL, then the read data

may be corrupted. This is due to the fact that the data

being read is the output value and not the DAC register

value. The LAT pin transition causes an update of the

output value. Based on the DAC output value, the

DACx register value, and the Command bit where the

LAT pin transitions, the value being read could be

corrupted.

If LAT pin transitions occur during a read of the DACx

performed until the two most recent read values match.

Then the most recent read data is good.

7.2.2

SINGLE READ

The Read command operation requires that the

CS pin be in the active state (VIL). Typically, the CS pin

will be in the inactive state (VIH) and is driven to the

active state (VIL). The 24-bit Read command

(Command Byte and Data Byte) is then clocked in on

the SCK and SDI pins. The SDO pin starts driving data

on the 8th bit (CMDERR bit), and the addressed data

comes out on the 9th through 24th clocks.

FIGURE 7-7:

Read Command - SDI and SDO States.

Note 1:

During device communication, if the

Device Address/Command combination

is invalid or an unimplemented Address is

specified, then the MCP48FEBXX will

command error that byte. To reset the

SPI state machine, the CS pin must be

driven to the VIH state.

If the LAT pin is High (VIH), reads of the

volatile DAC Register read the output

value, not the internal register.

The read commands operate the same

regardless

the

state

the

High-Voltage Command (HVC) signal.

X X X X X X X XXXXXXXXX

11111111

ddddddddd Valid (1)

1111111

0Invalid (2, 3)

SDI

SDO

Note 1:

If a valid Address/Command occurs, then the data bits are dependent on the resolution of the device.

12-bit = D11:D00, 10-bit = D09:D00, and 8-bit = D07:D00. Data is right justified for ease of Host Controller

operation (i.e., no data manipulation before transmitting the desired value).

Unimplemented data bits (D15:D12 on 12-bit device, D15:D10 on 10-bit device, D15:D08 on 8-bit device)

will be output as ‘1’.

If an Error condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR condition

is cleared (the CS pin is forced to the inactive state).

Address

Data bits (8-, 10, or 12-bits)

Command

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