| 数据搜索系统,热门电子元器件搜索 |
|
PIMXRT516SCVP2A 数据表(PDF) 55 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
PIMXRT516SCVP2A 数据表(HTML) 55 Page - NXP Semiconductors |
|
55 / 124 page ![]() Electrical characteristics i.MX RT1160 Crossover Processors Data Sheet for Extended Industrial Products, Rev. 0, 04/2021 NXP Semiconductors 55 4.5.1 SEMC specifications The following sections provide information on SEMC interface. Measurements are with a load of 15 pf and an input slew rate of 1 V/ns. 4.5.1.1 SEMC output timing There are ASYNC and SYNC modes for SEMC output timing. 4.5.1.1.1 SEMC output timing in ASYNC mode Table 45 shows SEMC output timing in ASYNC mode. Figure 15 shows the output timing in ASYNC mode. Table 45. SEMC output timing in ASYNC mode Symbol Parameter Min. Max. Unit Comment Frequency of operation — 200 MHz TCK Internal clock period 5 — ns TAVO Address output valid time — 2 ns These timing parameters apply to Address and ADV# for NOR/PSRAM in ASYNC mode. TAHO Address output hold time (TCK - 2) 1 1 Address output hold time is configurable by SEMC_*CR0.AH. AH field setting value is 0x0 in above table. When AH is set with value N, TAHO min time should be ((N + 1) x TCK). See the i.MX RT1160 Reference Manual (IMXRT1160RM) for more detail about SEMC_*CR0.AH register field. —ns TADVL Active low time (TCK - 1) 2 2 ADV# low time is configurable by SEMC_*CR0.AS. AS field setting value is 0x0 in above table. When AS is set with value N, TADL min time should be ((N + 1) x TCK - 1). See the i.MX RT1160 Reference Manual (IMXRT1160RM) for more detail about SEMC_*CR0.AS register field. TDVO Data output valid time — 2 ns These timing parameters apply to Data/CLE/ALE and WE# for NAND, apply to Data/DM/CRE for NOR/PSRAM, apply to Data/DCX and WRX for DBI interface. TDHO Data output hold time (TCK - 2) 3 3 Data output hold time is configurable by SEMC_*CR0.WEH. WEH field setting value is 0x0 in above table. When WEH is set with value N, TDHO min time should be ((N + 1) x TCK). See the i.MX RT1160 Reference Manual (IMXRT1160RM) for more detail about SEMC_*CR0.WEH register field. —ns TWEL WE# low time (TCK - 1) 4 4 WE# low time is configurable by SEMC_*CR0.WEL. WEL field setting value is 0x0 in above table. When WEL is set with value N, TWEL min time should be ((N + 1) x TCK - 1). See the i.MX RT1160 Reference Manual (IMXRT1160RM) for more detail about SEMC_*CR0.WEL register field. ns |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |