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PIMXRT516SCVP2A 数据表(PDF) 68 Page - NXP Semiconductors |
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PIMXRT516SCVP2A 数据表(HTML) 68 Page - NXP Semiconductors |
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68 / 124 page  i.MX RT1160 Crossover Processors Data Sheet for Extended Industrial Products, Rev. 0, 04/2021 68 NXP Semiconductors Electrical characteristics (VSYNC), then CSI_HSYNC (HSYNC) is asserted and holds for the entire line. The pixel clock, CSI_PIXCLK (PIXCLK), is valid as long as HSYNC is asserted. Figure 27. CSI Gated clock mode—sensor data at falling edge, latch data at rising edge Figure 28. CSI Gated clock mode—sensor data at rising edge, latch data at falling edge Table 68. CSI gated clock mode timing parameters ID Parameter Symbol Min. Max. Units P1 CSI_VSYNC to CSI_HSYNC time tV2H 33.5 — ns P2 CSI_HSYNC setup time tHsu 2.6 — ns P3 CSI DATA setup time tDsu 2.6 — ns CSI_PIXCLK CSI_VSYNC CSI_DATA[23:00] P5 P1 P3 P4 CSI_HSYNC P2 P6 P7 CSI_PIXCLK CSI_VSYNC CSI_DATA[23:00] P6 P1 P3 P4 CSI_HSYNC P2 P5 P7 |
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