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ADCA3270ACEZ-R7 数据表(PDF) 11 Page - Analog Devices |
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ADCA3270ACEZ-R7 数据表(HTML) 11 Page - Analog Devices |
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11 / 14 page ![]() Data Sheet ADCA3270 Rev. 0 | Page 11 of 14 APPLICATIONS INFORMATION ADCA3270 TEMPERATURE SENSE MONITOR The ADCA3270 has an internally mounted, negative temperature coefficient (NTC) thermistor that, when used as the bottom of a resistive voltage divider, provides an output voltage that is correlated to the ground temperature at the TPADDLE of the LGA_CAV package. When configured as shown in Figure 16, the typical relationship between VTSEN and TPADDLE results in what is shown in Figure 17. NTC ADCA3270 3.3kΩ 5V REFERENCE VTSEN 8 Figure 16. Recommended NTC Configuration 95 90 85 80 75 65 70 60 55 50 45 40 35 30 25 20 0.6 0.8 1.0 1.4 1.6 1.8 1.2 2.0 2.2 2.4 VTSEN (V) Figure 17. TPADDLE vs. VTSEN THERMAL CONSIDERATIONS The ADCA3270 is packaged in a thermally efficient, 9-terminal chip array small outline no lead cavity [LGA_CAV]. The thermal resistance from θJC is 2.9°C/W, where the case is defined by the exposed paddle on the bottom of the package. For the best thermal performance, it is recommended that as many thermal vias as possible be added under the exposed paddle of the LGA_CAV package. For optimal performance, it is recommended that these vias be filled with a paste that has high thermal conductivity. It is also recommended that the array of vias under the ADCA3270 interface to an external heat sink such as a pedestal on the system chassis. SOLDERING INFORMATION AND RECOMMENDED PCB LAND PATTERN Figure 18 shows the recommended land pattern for the ADCA3270. To minimize thermal impedance, the exposed paddle on the 9.00 mm × 8.00 mm LGA_CAV is soldered to a ground plane along with Pin 2, Pin 3, and Pin 6. To improve thermal dissipation, 188 thermal vias are arranged in an array under the exposed paddle. The array consists of alternating rows of 13 vias and 12 vias, maximizing the number of vias within the area. The area under the paddle is also tied to ground on the bottom layer of the PCB. If multiple ground layers exist, tie these layers together by the vias. The external layer of the PCB must be a minimum of 2 oz. copper. The minimum average plated hole wall thickness of the vias must not be less than 0.001 inch, and it is recommended that the vias be filled with a conductive paste, such as Tatsuta AE3030, and plated over. The full recommended PCB footprint design is shown in Figure 19. Figure 18. Recommended Land Pattern For further information on optimizing the thermal performance while using the ADCA3270, refer to the AN-1604 Application Note, Thermal Management Calculations for RF Amplifiers in LFCSP and Flange Packages. |
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