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FXLS8967AFR3 数据表(PDF) 29 Page - NXP Semiconductors |
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FXLS8967AFR3 数据表(HTML) 29 Page - NXP Semiconductors |
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29 / 98 page  NXP Semiconductors FXLS8967AF 3-Axis Low-g Accelerometer Auto-increment Address Name Type Register Address F_READ = 0 F_READ = 1 Default Values BT_MODE = GND/[VDD] Comment BUF _Y_LSB[1][3][4] R 0Eh 0Fh 10h/0Ch/0Eh — Head/Tail sample of output buffer Y-axis LSB - buf_y_out[7:0] when SENS_CONFIG2[LE_BE] = 0 and buf_y_out[11:4] when SENS_CONFIG2[ LE_BE ] = 1. When SENS_CONFIG5[Y_DIS] = 1, this register is skipped over by the auto-increment mechanism. BUF _Y_MSB[1][3][4] R 0Fh 10h/0Ch/0Eh — Head/Tail sample of output buffer Y-axis MSB - buf_Y_out[11:8] when SENS_CONFIG2[LE_BE] = 0 and buf_y_out[3:0] when SENS_CONFIG2[LE_BE] = 1. When SENS_CONFIG5[Y_DIS] = 1, this register is skipped over by the auto-increment mechanism. BUF_Z_LSB[1][3][4] R 10h 11h 0Ch/0Eh/10h — Head/Tail sample of output buffer Z-axis LSB - buf_z_out[7:0] when SENS_CONFIG2[LE_BE] = 0 and buf_z_out[11:4] when SENS_CONFIG2[LE_BE] = 1. When SENS_CONFIG5[Z_DIS] = 1, this register is skipped over by the auto-increment mechanism. BUF_Z_MSB[1][3][4] R 11h 0Ch/0Eh/10h — Head/Tail sample of output buffer Z-axis MSB - buf_Z_out[11:8] when SENS_CONFIG2[LE_BE] = 0 and buf_z_out[3:0] when SENS_CONFIG2[LE_BE] = 1. When SENS_CONFIG5[Z_DIS] = 1, this register is skipped over by the auto-increment mechanism. Device identification PROD_REV R 12h 13h 13h Product revision number in BCD format [maj.min] with range 1.0 to 9.9 WHO_AM_I[1] R 13h 14h 87h 8-bit NXP unique sensor product ID. System status register SYS_MODE [1] [2] R 14h 15h 00h/[01h] Current system operating mode, buffer gate error flag, and buffer gate error sample count Device configuration and control registers SENS_CONFIG1 [1] [5] R/W 15h 16h 00h/[03h] Full-scale range selection, self-test axis, and polarity selection, soft reset, Active mode enable. SENS_CONFIG2 [1] [5] R/W 16h 17h 00h WAKE and SLEEP power mode selections, little/big endian output mode, auto-increment control, fast read enable. SENS_CONFIG3 [1] [5] R/W 17h 18h 00h/[C0h] WAKE and SLEEP mode ODR and decimation selections SENS_CONFIG4 [1] [5] R/W 18h 19h 01h Auto-WAKE/SLEEP interrupt source enable bits, interrupt output pin logic polarity, and driver type, external trigger input function enable SENS_CONFIG5 [1] [5] R/W 19h 1Ah 00h/[00h] Auto-increment mechanism disable bits for X/Y/Z axis data; Hibernate mode enable WAKE_IDLE _LSB [1] [5] R/W 1Ah 1Bh 00h LSB of 12-bit user programmable WAKE mode idle time - wake_idle[7:0] WAKE_IDLE_MSB [1] [5] R/W 1Bh 1Ch 00h MSB of 12-bit user programmable WAKE mode idle time - wake_idle[11:8] SLEEP_IDLE_LSB [1] [5] R/W 1Ch 1Dh 00h LSB of 12-bit user programmable SLEEP mode idle time - sleep_idle[7:0] SLEEP_IDLE_MSB [1] [5] R/W 1Dh 1Eh 00h MSB of 12-bit user programmable SLEEP mode idle time - sleep_idle[11:8] ASLP_COUNT_LSB [1] [5] R/W 1Eh 1Fh 00h LSB of inactivity time-out count value used for transitioning into Auto-SLEEP mode: aslp_ count[7:0]. In order to enable the Auto-WAKE/SLEEP feature, the value written to this register must be ≥ 1. ASLP_COUNT_MSB [1] [5] R/W 1Fh 20h 00h MSB of inactivity time-out count value used for transitioning into Auto-SLEEP mode: aslp_ count[11:8] Table 20. Register address map...continued FXLS8967AF All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Objective data sheet Rev. 1 — 27 April 2021 29 / 98 |
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