24CS512-ESLASHP datasheet(11/66 Pages) MICROCHIP

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DS20005769C-page 11

24CS512

3.3.1

VALID DEVICE ADDRESS BYTE

INPUTS

The 24CS512 will respond to two different device type

identifiers, as well as two reserved host codes as

shown in Table 3-2.

3.3.1.1

Read/Write Select Bit

The eighth bit (bit 0) of the device address byte is the

Read/Write Select (R/W) bit. A read operation is initi-

ated if this bit is a logic ‘1’ and a write operation is initi-

ated if this bit is a logic ‘0’.

Upon the successful comparison of the device address

byte, the 24CS512 will respond. If a valid comparison

is not made, the device will not respond and will return

to a standby state.

TABLE 3-2:

TABLE OF VALID DEVICE ADDRESS BYTES

Access Region

Device Address

Byte Type

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

512-Kbit EEPROM(1)

Device Type Identifier +

Hardware Address

R/W

Security Register(1,2)

R/W

Configuration Register(1,2)

R/W

Manufacturer Identification(3)

Reserved Host Code

111

R/W

High-Speed (HS) Mode(4)

001

Note 1: The hardware client address bits must be set to logic ‘0’ when using the SOT-23 package.

2: Accessing the Security or Configuration register is only possible if any sequence or command to the main

EEPROM (if one has been sent) has been properly terminated with a Stop condition. Without proper termi-

nation of the previous sequence, all communications with the Security or Configuration registers will not

execute successfully.

3: See Section 11.0 “Manufacturer Identification Register” for details.

4: See Section 8.0 “High-Speed Mode” for details.

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