24CS512-ESLASHP datasheet(17/66 Pages) MICROCHIP

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DS20005769C-page 17

24CS512

6.3

Internal Writing Methodology

The 24CS512 incorporates a built-in Error Correction

Code (ECC) logic scheme. The EEPROM array is inter-

nally organized as a group of four connected 8-bit bytes,

plus an additional six ECC (Error Correction Code) bits

of EEPROM. These 38 bits are referred to as the internal

physical data word. During a read operation, the ECC

logic compares each 4-byte physical data word with its

corresponding six ECC bits. If a single bit out of the

4-byte region reads incorrectly, the ECC logic will detect

the bad bit and replace it with the correct value before

the data is serially clocked out. This architecture signifi-

cantly improves the reliability of the 24CS512 compared

to an implementation that does not utilize ECC.

It is important to note that data is always physically

written to the part at the internal physical data word level,

regardless of the number of bytes written. Writing single

bytes is still possible with the byte write operation, but

internally, the other three bytes within that 4-byte loca-

tion where the single byte was written, along with the six

ECC bits, will be updated. Due to this architecture, the

write endurance is rated at the internal physical data

word level (4-byte word).

The system designer needs to optimize the application

writing algorithms to observe these internal word

boundaries in order to reach the write cycle endurance

rating.

6.4

Write Cycle Timing

The length of the self-timed write cycle, or TWC, is

defined as the amount of time from the Stop condition,

that begins the internal write operation, to the Start con-

dition of the first device address byte sent to the

24CS512 that it subsequently responds to with an ACK

(see Figure 6-3).

During the internally self-timed write cycle, any

attempts to access the device will be ignored.

FIGURE 6-3:

WRITE CYCLE TIMING

TWC

Stop

Condition

Start

Condition

Data Word n

ACK

SDA

Stop

Condition

SCL

ACK

First Acknowledge from the device to

a valid device address sequence after

write cycle is initiated. The minimum

Twc can only be determined through

the use of an ACK polling routine.

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