PLL650-06

Network LAN Clock

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 4

2. AC Specifications

PARAMETERS

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Input Frequency

10

25

27

MHz

Output Rise Time

0.8V to 2.0V with no load

1.5

ns

Output Fall Time

2.0V to 0.8V with no load

1.5

ns

Duty Cycle

45

50

55

%

Max. Absolute Jitter

Short term

±150

ps

Max. Jitter, cycle to cycle

80

ps

3. DC Specifications

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Operating Voltage

2.97

3.63

V

Input High Voltage

V

Input Low Voltage

V

Input High Voltage

For all Tri-level input

V

Input Low Voltage

For all Tri-level input

0.5

V

Input High Voltage

For all normal input

2

V

Input Low Voltage

For all normal input

0.8

V

Output High Voltage

2.4

V

Output Low Voltage

0.4

V

Output High Voltage At

CMOS Level

V

Operating Supply Current

No Load

35

mA

Short-circuit Current

±50

mA

Nominal output current*

CMOS output level

35

40

mA

Nominal output current*

TTL output level

20

25

mA

Internal pull-up resistor

Pins 5,7

60

k

Ω

Internal pull-up resistor

Pin 2

120

k

Ω

*: Output strengths are doubled (i.e. min. CMOS level is 70mA, typ. CMOS level is 80mA) on pin 6 (output for 75MHz or 66.6MHz)