PLL650-06

Network LAN Clock

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1

FEATURES

• Full CMOS output swing with 40-mA output drive

capability. 25-mA output drive at TTL level.

• Advanced, low power, sub-micron CMOS processes.

• 25MHz fundamental crystal or clock input.

• One output fixed at 50MHz

• One selectable frequency output of 66.6 or 75MHz (with

Double Drive Strength output).

• Zero PPM synthesis error in all clocks.

• Ideal for Network switches.

• 3.3V operation.

•

DESCRIPTION

The PLL 650-06 is a low cost, low jitter, and high

performance clock synthesizer. Using PhaseLink’s

proprietary analog Phase Locked Loop techniques, this

device can produce one 50MHz output clock and one

selectable 75MHz or 66.6MHz output clock from a single

low cost 25.0MHz crystal. This makes the PLL650-06 ideal

for networking applications.

PIN CONFIGURATION

*: bi-directional pin

+ : double strength output

FREQUENCY TABLE

FS

Pin 6

0

75MHz

1

66.6MHz

BLOCK DIAGRAM

XTAL

OSC

50MHz

XIN

XOUT

75MHz/66MHz

Control

Logic

FS

1

1

2

3

45

6

7

8

XIN

XOUT

GND

50MHz/FS*

VDD

VDD

GND