ADPA7006CHIP datasheet(16/24 Pages) AD

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ADPA7006CHIP

Data Sheet

Rev. 0 | Page 16 of 24

APPLICATIONS INFORMATION

The ADPA7006CHIP is a GaAs, pHEMT, MMIC power

amplifier. Capacitive bypassing is required for all primary and

alternate VGGx and VDDxx pads.

VGGA and VGGB are the gate bias pads for the cascaded amplifiers.

VDD1A, VDD1B, VDD2A, VDD2B, VDD3A, VDD3B, VDD4A, and VDD4B are the

drain bias pads for the cascaded amplifiers.

All measurements for this device were taken using the typical

application circuit (see Figure 62) and were configured as shown

in the assembly diagram (see Figure 64 and Figure 65).

The recommended bias sequence during power-up is as follows:

Connect GND to RF and dc ground.

Set the primary gate bias voltages, VGGA and VGGB, to −1.5 V.

Set all the drain bias voltages, VDDxx, to 5 V.

Increase the gate bias voltage to achieve a quiescent

current, and set IDQ = 800 mA.

Apply the RF signal.

The recommended bias sequence during power-down is as

follows:

Turn off the RF signal.

Decrease the primary gate bias voltage, VGGA, to −1.5 V to

achieve IDQ = 0 mA (approximately).

Decrease all drain bias voltages to 0 V.

Increase the gate bias voltage to 0 V.

Simplified bias pad connections to dedicated gain stages and

dependence and independence among pads are shown in

Figure 51.

The VDD = 5 V and IDQ = 800 mA bias conditions are recom-

mended to optimize overall performance. Unless otherwise

noted, the data shown was taken using the recommended bias

conditions. Operation of the ADPA7006CHIP at different bias

conditions may provide performance that differs from what is

shown in the nominal (VDD = 5 V and IDQ = 800 mA) typical

performance characteristic figures. Biasing the ADPA7006CHIP

for higher drain current typically results in higher P1dB, output

IP3, and gain at the expense of increased power consumption.

MOUNTING AND BONDING TECHNIQUES FOR

MILLIMETERWAVE GaAs MMICS

Attach the die directly to the ground plane with conductive

epoxy (see the Handling Precautions section, the Mounting

section, and the Wire Bonding section).

Microstrip, 50 Ω transmission lines on 0.127 mm thick alumina

thin film substrates are recommended for bringing the RF to

and from the chip. Raise the die 0.075 mm to ensure that the

surface of the die is coplanar with the surface of the substrate.

Place the microstrip substrates as close to the die as possible to

minimize ribbon bond length. Typical die to substrate spacing

is 0.076 mm to 0.152 mm. To ensure wideband matching, a

15 fF capacitive stub is recommended on the PCB before the

ribbon bond.

MMIC

PCB BOARD

50Ω

TRANSMISSION LINE

MATCHING STUB/BONDPAD

SHUNT CAPACITANCE = 15fF

3mil GOLD

RIBBON

3mil GAP

RFIN

Figure 52. High Frequency Input Wideband Matching

Table 8. Power Selection Table1, 2

IDQ (mA)

Gain (dB)

P1dB (dBm)

Output IP3 (dBm)

PDISS (W)

VGGx (V)

700

22.5

29.5

39.2

3.5

−0.7

800

22.9

29.6

37.5

4.0

−0.66

900

23.4

29.7

35.6

4.5

−0.62

1 Data taken at the following nominal bias conditions: VDD = 5 V, T = 25°C.

2 Adjust VGGA from −2 V to 0 V to achieve the desired drain current.

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