ADPA7006CHIP datasheet(20/24 Pages) AD

20 / 24 page

ADPA7006CHIP

Data Sheet

Rev. 0 | Page 20 of 24

HMC980LP4E BIAS SEQUENCE

The dc supply sequence described in this section is required to

prevent damage to the HMC980LP4E when using the device to

control the ADPA7006CHIP.

Power-Up Sequence

The power-up sequence for the HMC980LP4E is as follows:

VDIG = 3.3 V.

S0 = 3.3 V.

VDD = 5.77 V.

VNEG = −1.5 V (this step is unnecessary if using an

internally generated voltage).

EN = 3.3 V (transition from 0 V to 3.3 V turns on VGATE

and VDRAIN)

Power-Down Sequence

The power-down sequence for the HMC980LP4E is as follows:

EN = 0 V (transition from 3.3 V to 0 V turns off VDRAIN and

VGATE).

VNEG = 0 V (unnecessary if using internally generated

voltage).

VDD = 0 V.

S0 = 0 V.

VDIG = 0 V.

After the HMC980LP4E bias control circuit is set up, toggle

the bias to the ADPA7006CHIP on or off by applying 3.3 V or

0 V, respectively, to the EN pad. At EN = 3.3 V, VGATE drops to

−1.5 V and VDRAIN turns on at 5 V. VGATE then rises until IDRAIN =

800 mA, and the closed control loop regulates IDRAIN at 900 mA.

When EN = 0 V, VDRAIN is set to −1.5 V and VDRAIN is set to 0 V.

CH1 2V

CH3 2V

CH2 1V

CH4 2V

M20.0ms

A CH1

1.12V

50.00%

VDD

VDRAIN

VGATE

Figure 57. Turn On HMC980LP4E Outputs to ADPA7006CHIP

CH1 2V

CH3 2V

CH2 1V

CH4 2V

M20.0ms

A CH1

1.12V

50.00%

VDD

VDRAIN

VGATE

Figure 58. Turn Off HMC980LP4E Outputs to ADPA7006CHIP

CONSTANT DRAIN CURRENT BIASING vs.

CONSTANT GATE VOLTAGE BIASING

The HMC980LP4E uses closed-loop feedback to continuously

adjust VGATE to maintain a constant gate current bias over dc

supply variation, temperature, and device to device variation. In

addition, constant drain current bias is the optimum method

for reducing time in calibration procedures and for maintaining

consistent performance over time. By comparing with a constant

gate voltage bias where the current is driven to increase when

RF power is applied, a slightly lower output P1dB is seen with a

constant drain current bias. This output P1db is shown in

Figure 62, where the RF performance is slightly lower than

constant gate voltage bias operation due to a lower drain current

at high input powers as the device reaches 1dB compression.

The output P1dB performance for constant drain current bias

can be increased toward constant gate voltage bias performance

by increasing the set current toward the IDD it reaches under RF

drive in the constant gate voltage bias condition, as shown in

Figure 62. The limit of increasing IDQ under the constant current

operation is set by thermal limitations which can be found in

the absolute maximum ratings table from the amplifier data

sheet with the maximum power dissipation specification. As the

IDD increase continues, the actual output P1dB does not continue to

increase indefinitely and the power dissipation increases. Therefore,

take the exchange between power dissipation and output P1dB

performance into consideration when using constant drain

current biasing.

ADPA7006CHIP 数据表(PDF) 20 Page - Analog Devices

ADPA7006CHIP 数据表(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

数据表下载