PLL702-06

Clock Generator for Printer Applications

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

www.phaselin.com

Rev.

10/26/05

LAYOUT RECOMMENDATION

The following is the recommended layout for PhaseLink’s PLL702-06 in 16-pin SOIC package.

PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION

The following guidelines are to assist you with a performance optimized PCB design:

- Keep all the PCB traces to PL702-06 as short as

possible, as well as keeping all other traces as far

away from it as possible.

- Place the crystal as close as possible to both crystal

pins of the device. This will reduce the cross-talk

between the crystal and the other signals.

- Separate crystal pin traces from the other signals on

the PCB, but allow ample distance between the two

crystal pin traces.

- Place 0.01µF~0.1µF decoupling capacitors between

VDDs and GNDs (see above diagram), on the

component side of the PCB, close to the VDD pins. It

is not recommended to place these components on

the backside of the PCB. Going through vias will

reduce the signal integrity, causing additional jitter

and phase noise.

- It is highly recommended to keep the VDD and GND

traces as short as possible.

- When connecting long traces (> 1 inch) to a CMOS

output, it is important to design the traces as a

transmission line or ‘stripline’, to avoid reflections or

ringing. In this case, the CMOS output needs to be

matched to the trace impedance. Usually ‘striplines’

are designed for 50Ω impedance and CMOS outputs

usually have lower than 50Ω impedance so matching

can be achieved by adding a resistor in series with

the CMOS output pin to the ‘stripline’ trace.

- Please contact PhaseLink for the application note on

how to design outputs driving long traces or the

Gerber files for the PL702-06 layout.

- Please contact PhaseLink for a detailed crystal spec.