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AT25SL321 数据表(PDF) 13 Page - Dialog Semiconductor |
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AT25SL321 数据表(HTML) 13 Page - Dialog Semiconductor |
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13 / 82 page  12 AT25SL321 DS-25SL321–112H–2020-10 7. Status Register The Read Status Register instruction can be used to provide status on the availability of the Flash memory array, if the device is write enabled or disabled the state of write protection and the Quad SPI setting. The Write Status Register instruction can be used to configure the devices writes protection features and Quad SPI setting. Write access to the Status Register is controlled by in some cases of the WP pin. 7.1 Busy BUSY is a read-only bit in the Status register (S0) that hardware sets to 1 whenever the device is executing a Page Program, Erase, Write Status Register or Write Security Register instruction. During this time the device ignores further instructions, except for the Read Status Register and Erase / Program Suspend instruction (see tW, tPP, tSE, tBE1, tBE2, and tCE in AC Characteristics). When the Program, Erase, Write Status Register or Write Security Register instruction has completed, hardware clears the BUSY bit to 0, indicating the device is ready for further instructions. 7.2 Write Enable Latch (WEL) The Write Enable Latch (WEL) is a read-only bit in the Status register (S1) that hardware sets to 1 after executing a Write Enable (06h) instruction. Hardware clears the WEL bit when the device is write disabled. A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Erase, and Write Status Register. 7.3 Status Register Protect (SRP1, SRP0) The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the Status register (S8 and S7). The SRP bits control the method of write protection. These include software protection, hardware protection, power supply lock-down or one time programmable (OTP) protection. Table 7-1. Status Register-1 S7 S6 S5 S4 S3 S2 S1 S0 SRP (R) (R) (R) (R) (R)0 WEL BUSY Status Register Protect 0 (Non- Volatile) Reserved Reserved Reserved Reserved Reserved Write Enable Latch Erase or Write in Progress Table 7-2. Status Register-2 S15 S14 S13 S12 S11 S10 S9 S8 SUS (R) (R) (R) (R) (R) QE SRP1 Suspend Status Reserved Reserved Reserved Reserved Reserved Quad Enable (Non- Volatile) Status Register Protect 1 (Non- Volatile) |
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