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AT25SL321

DS-25SL321–112H–2020-10

8.17 Block Erase (20h)

The Block Erase instruction is to erase the data of the selected sector as being ‘1’. The instruction is used for 4K-

byte Block. Prior to the Block Erase Instruction, the Write Enable instruction must be issued. The instruction is

initiated by driving the CS pin low and shifting the instruction code 20h followed a 24-bit Block address (A23-A0).

See Figure 8-26 and Figure 8-27. The CS pin must go high after the eighth bit of the last byte has been latched in,

otherwise, the Block Erase instruction can not be executed. After CS goes high, the self-timed Block Erase

instruction commences for a time duration of tSE. See Section 9.8, AC Electrical Characteristics.

While the Block Erase cycle is in progress, the Read Status Register instruction can still be accessed for checking

the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is

finished and the device is ready to accept other instructions again. When the BUSY bit is asserted, the Write

Enable Latch (WEL) bit in the Status Register is cleared to 0.

Figure 8-26. Block Erase Instruction (SPI Mode)

Figure 8-27. Block Erase Instruction (QPI Mode)

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