SCIMX356BVMB datasheet(72/147 Pages) NXP

72 / 147 page

i.MX35 Applications Processors for Automotive Products, Rev. 10

Freescale Semiconductor

Figure 50 depicts the synchronous display interface timing for access level, and Table 56 lists the timing

parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the

DI_DISP3_TIME_CONF Register.

Figure 50. Synchronous Display Interface Timing Diagram—Access Level

IP9

Horizontal blank interval 1

Thbi1

BGXP

× Tdpcp

IP10

Horizontal blank interval 2

Thbi2

(SCREEN_WIDTH – BGXP – FW)

× Tdpcp

IP11

HSYNC delay

Thsd

H_SYNC_DELAY

× Tdpcp

IP12

Screen height

Tsh

(SCREEN_HEIGHT + 1)

× Tsw

IP13

VSYNC width

Tvsw

if V_SYNC_WIDTH_L = 0 than

(V_SYNC_WIDTH + 1)

× Tdpcp

else

(V_SYNC_WIDTH + 1)

× Tsw

IP14

Vertical blank interval 1

Tvbi1

BGYP

× Tsw

IP15

Vertical blank interval 2

Tvbi2

(SCREEN_HEIGHT – BGYP – FH)

× Tsw

1 Display interface clock period immediate value

Display interface clock period average value.

Table 55. Synchronous Display Interface Timing Parameters—Pixel Level (continued)

Parameter

Symbol

Value

Units

Tdicp

HSP_CLK

DISP3_IF_CLK_PER_WR

HSP_CLK_PERIOD

------------------------------------------------------------------

⋅

IP19

DISPB_D3_CLK

DISPB_DATA

IP18

IP20

DISPB_D3_VSYNC

IP17

IP16

DISPB_D3_DRDY

DISPB_D3_HSYNC

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