PLL702-05

Low EMI Peripheral Clock Generator for Notebook

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991

www.phaselink.com

Rev 08/12/04 Page 2

PIN DESCRIPTIONS

Name

Pin#

Type

Description

XIN

1

I

Crystal input: accepts either 24.576MHz or 14.31818MHz fundamental crystal (CL =

20pF, parallel resonant mode, +/-20ppm). On-chip load capacitors: no external load

capacitors required. (See the table #4 )

XOUT

2

O

Crystal output.

VSS

3,6

P

Ground connection.

24.576MHz/SST0

4

B

Bi-directional and Tri-Level pin. Upon power-on, the value of SST0 is latched in and

used to select the SST control (see Spread Spectrum selection table 1). Tri level input:

M = Do not connect, 1 = Pull up, 0 = Pull down. After power-up this pin acts as

24.576MHz output clock.

25MHzx2

5

O

25MHz Ethernet output clock (double drive strength).

27_14.318MHz/XTAL_SEL

7

B

Bi-directional pin. Upon power-on, the value of XTAL_SEL is latched in and used to set

the input crystal frequency (24.575MHz or 14.31818MHz). Set XTAL_SEL to 0 (default)

for 24.576MHz input crystal, set XTAL_SEL to 1 for 14.31818MHz input crystal (see

Crystal Selection Table on page 1). . After power-up this pin acts as 27MHz output

(with 24.576MHz crystal) or as 14.31818MHz pass through clock (with 14.31818MHz

crystal), depending on the input crystal.

The 27MHz output can be modulated for low EMI using Spread Spectrum.

VDD

8

P

3.3V power supply for 27MHz, oscillator, analog core and digital circuitry.

FUNCTIONAL DESCRIPTION

Tri-level and two-level inputs

In order to reduce pin usage, the PLL702-05 uses tri-level input pins. These pins allow 3 levels for input selection: namely, 0 =

Connect to GND, 1 = Connect to VDD, M = Do not connect. Thus, unlike the two-level selection pins, the tri-level input pins are

in the “M” (mid) state when not connected. In order to connect a tri-level pin to a logical “zero”, the pin must be connected to

GND. Likewise, in order to connect to a logical “one”, the pin must be connected to VDD.

Connecting a bi-directional pin

The PLL702-05 also uses bi-directional pins. The same pin serves as input upon power-up, and as output as soon as the inputs

have been latched. The value of the input is latched-in upon power-up. Depending on the pin (see pin description), the input can

be tri-level or a standard two-level. Unlike unidirectional pins, bi-directional pins cannot be connected directly to GND or VDD in

order to set the input to "0" or "1", since the pin also needs to serve as output. In the case of two level input pins, an internal pull-

up resistor is present. This allows a default value to be set when no external pull down resistor is connected between the pin

and GND (by definition, a tri-level input has a the default value of "M" (mid) if it is not connected). In order to connect a bi-

directional pin to a non-default value, the input must be connected to GND or VDD through an external pull-down/pull-up

resistor.

Note: when the output load presents a low impedance in comparison to the internal pull-up resistor, the internal pull-up resistor

may not be sufficient to pull the input up to a logical “one”, and an external pull-up resistor may be required.

For bi-directional inputs, the external loading resistor between the pin and GND has to be sufficiently small (compared to the

internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical “zero”). In order to avoid loading effects when the

pin serves as output, the value of the external pull-down resistor should however be kept as large as possible. In general, it is