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ADCLK914BCPZ-R2 数据表(PDF) 3 Page - Analog Devices

部件名 ADCLK914BCPZ-R2
功能描述  Ultrafast, SiGe, Open-Collector HVDS Clock/Data Buffer
PDF  11 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADCLK914BCPZ-R2 数据表(HTML) 3 Page - Analog Devices

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Data Sheet
ADCLK914
Rev. B | Page 3 of 11
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCC = 3.3 V, VEE = 0 V, TA = −40°C to +125°C. All outputs terminated through 50 Ω to VCC, unless otherwise noted.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DC INPUT CHARACTERISTICS
Input High Voltage
VIH
VEE + 1.65
VCC
V
Input Low Voltage
VIL
VEE
VCC − 0.2
V
Input Differential Range
VID
0.2
3.4
V p-p
TA = −40°C to +85°C
(±1.7 V between input pins)
0.2
2.8
V p-p
TA = 85°C to 125°C
(±1.4 V between input pins)
Input Capacitance
CIN
0.4
pF
Input Resistance
50
Ω
Differential Mode
100
Ω
Common Mode
50
kΩ
Open termination
Input Bias Current
20
µA
DC OUTPUT CHARACTERISTICS
Output High Voltage
VOH
VCC − 0.55
VCC − 0.40
VCC − 0.25
V
Output Low Voltage
VOL
VCC − 2.75
VCC − 2.35
VCC − 1.9
V
Output Differential Range
VOD
1.54
1.95
2.22
V
Reference Voltage
VREF
Output Voltage
(VCC + 1)/2
V
−500 μA to +500 μA
Output Resistance
250
Ω
AC PERFORMANCE
Operating Frequency
7.5
GHz
>1.1 V differential output swing,
VCC = 3.3 V ± 10%
Propagation Delay
tPD
127
158
202
ps
VCC = 3.3 V ± 10%,VICM = VREF,
VID = 1.6 V p-p
Propagation Delay Temperature
Coefficient
140
fs/°C
Propagation Delay Skew (Device
to Device)
65
ps
VID = 1.6 V p-p
Output Rise Time
tR
100
125
ps
20%/80%
Output Fall Time
tF
80
95
ps
80%/20%
Wideband Random Jitter1
RJ
110
fs rms
VID = 1.6 V p-p, 6 V/ns, VICM = 1.85 V
Additive Phase Noise
622.08 MHz
−132
dBc/Hz
@10 Hz offset
−143
dBc/Hz
@100 Hz offset
−151
dBc/Hz
@1 kHz offset
−156
dBc/Hz
@10 kHz offset
−157
dBc/Hz
@100 kHz offset
−156
dBc/Hz
>1 MHz offset
245.76 MHz
−133
dBc/Hz
@10 Hz offset
−143
dBc/Hz
@100 Hz offset
−153
dBc/Hz
@1 kHz offset
−158
dBc/Hz
@10 kHz offset
−159
dBc/Hz
@100 kHz offset
−158
dBc/Hz
>1 MHz offset



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