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ADCLK914BCPZ-R2 数据表(PDF) 1 Page - Analog Devices |
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ADCLK914BCPZ-R2 数据表(HTML) 1 Page - Analog Devices |
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1 / 11 page ![]() Ultrafast, SiGe, Open-Collector HVDS Clock/Data Buffer Data Sheet ADCLK914 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2008–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES 7.5 GHz operating frequency 160 ps propagation delay 100 ps output rise/fall 110 fs random jitter On-chip input terminations Extended industrial temperature range: −40°C to +125°C 3.3 V power supply (VCC − VEE) APPLICATIONS Clock and data signal restoration High speed converter clocking Broadband communications Cellular infrastructure High speed line receivers ATE and high performance instrumentation Level shifting Threshold detection FUNCTIONAL BLOCK DIAGRAM D D Q VCC VEE VT Q VREF 50Ω 50Ω 50Ω 50Ω ADCLK914 Figure 1. GENERAL DESCRIPTION The ADCLK914 is an ultrafast clock/data buffer fabricated on the Analog Devices, Inc., proprietary, complementary bipolar (XFCB-3) silicon-germanium (SiGe) process. The ADCLK914 features high voltage differential signaling (HVDS) outputs suitable for driving the latest Analog Devices high speed digital- to-analog converters (DACs). The ADCLK914 has a single, differential open-collector output. The ADCLK914 buffer operates up to 7.5 GHz with a 160 ps propagation delay and adds only 110 fs random jitter (RJ). The input has a center tapped, 100 Ω, on-chip termination resistor and accepts LVPECL, CML, CMOS, LVTTL, or LVDS (ac-coupled only). A VREF pin is available for biasing ac-coupled inputs. The HVDS output stage is designed to directly drive 1.9 V each side into 50 Ω terminated to VCC for a total differential output swing of 3.8 V. The ADCLK914 is available in a 16-lead LFCSP. It is specified for operation over the extended industrial temperature range of −40°C to +125°C. |
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