STE2007 datasheet(22/62 Pages) STMICROELECTRONICS

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4 INTERFACE

STE2007

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Data transfer may be initiated only when the bus is not busy.

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During data transfer, the data line must remain stable whenever the clock line is high.

Changes in the data line while the clock line is high will be interpreted as a Start or

Stop Data Transfer condition (see below).

Accordingly, the following bus conditions have been defined:

BUS not busy: Both data and clock lines remain High.

Start Data Transfer: A change in the state of the data line, from High to Low, while the clock is

High, define the START condition.

Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock

signal is High, defines the STOP condition.

Data Valid: The state of the data line represents valid data when after a start condition, the

data line is stable for the duration of the High period of the clock signal. The data on the line

may be changed during the Low period of the clock signal. There is one clock pulse per bit of

data.

Each data transfer starts with a start condition and terminated with a stop condition. The

number of data bytes transferred between the start and the stop conditions is not limited. The

information is transmitted byte-wide and each receiver acknowledges with the ninth bit.

By definition, a device that gives out a message is called "transmitter", the receiving device that

gets the signals is called "receiver". The device that controls the message is called "master".

The devices that are controlled by the master are called "slaves"

Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This acknowledge

bit is a low level put on the bus by the receiver, whereas the master generates an extra

acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of each

byte. Also, a master receiver must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to pull

down the SDA_IN line during the acknowledge clock pulse. Of course, setup and hold time

must be taken into account. A master receiver must signal an end-of-data to the slave

transmitter by not generating an acknowledge on the last byte that has been clocked out of the

slave. In this case, the transmitter must leave the data line High to enable the master to

generate the STOP condition.

Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line.

Having the acknowledge output (SDAOUT) separated from the serial data line is advantageous

in Chip-On-Glass (COG) applications. In COG applications where the track resistance from the

SDAOUT pad to the system SDA line can be significant, a potential divider is generated by the

bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that during

the acknowledge cycle the STE2007 will not be able to create a valid logic 0 level. By splitting

the SDA input from the output the device could be used in a mode that ignores the

acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary

to minimize the track resistance from the SDACK pad to the system SDA line to guarantee a

valid LOW level.

To be compliant with the I2C-bus Hs-mode specification the STE2007 is able to detect the

special sequence "S00001xxx". After this sequence no acknowledge pulse is generated.

Since no internal modification are applied to work in Hs-mode, the device is able to work in Hs-

mode without detecting the master code.

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