DS31256_V01 datasheet(21/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

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Signal Name:

LHLDA (

LBG)

Signal Description:

Local Bus Hold Acknowledge (Local Bus Grant) (PCI Bridge Mode Only)

Signal Type:

Input

This input signal is sampled on the rising edge of LCLK to determine when the device has been granted access to

the bus. In Intel mode (LIM = 0), this is an active-high signal; in Motorola mode (LIM = 1) this is an active-low

signal. This signal is ignored and should be connected high when the local bus is in configuration mode

(LMS = 1). Also, in PCI bridge mode (LMS = 0), this signal should be wired deasserted when the local bus

arbitration is disabled through the LBBMC register.

Signal Name:

LHOLD (

LBR)

Signal Description:

Local Bus Hold (Local Bus Request) (PCI Bridge Mode Only)

Signal Type:

Output

This signal is asserted when the DS31256 is attempting to control the local bus. In Intel mode (LIM = 0), this

signal is an active-high signal; in Motorola mode (LIM = 1) this signal is an active-low signal. It is deasserted

concurrently with

LBGACK. This signal is tri-stated when the local bus is in configuration mode (LMS = 1) and

also in PCI bridge mode (LMS = 0) when the local bus arbitration is disabled through the LBBMC register.

Signal Name:

LBGACK

Signal Description:

Local Bus Grant Acknowledge (PCI Bridge Mode Only)

Signal Type:

Output (tri-state capable)

This active-low signal is asserted when the local bus hold-acknowledge/bus grant signal (LHLDA/

LBG) has been

detected and continues its assertion for a programmable (32 to 1,048,576) number of LCLKs, based on the local

bus arbitration timer setting in the LBBMC register. This signal is tri-stated when the local bus is in configuration

mode (LMS = 1).

Signal Name:

LBHE

Signal Description:

Local Bus Byte-High Enable (PCI Bridge Mode Only)

Signal Type:

Output (tri-state capable)

This active-low output signal is asserted when all 16 bits of the data bus (LD[15:0]) are active. It remains high if

only the lower 8 bits (LD[7:0)] are active. If bus arbitration is enabled through the LARBE control bit in the

LBBMC register, this signal is tri-stated when the local bus is not currently involved in a bus transaction and

driven when a bus transaction is active. When bus arbitration is disabled, this signal is always driven. This signal

remains in tri-state when the local bus is not involved in a bus transaction and is in configuration mode

(LMS = 1).

Signal Name:

LCLK

Signal Description:

Local Bus Clock (PCI Bridge Mode Only)

Signal Type:

Output (tri-state capable)

This signal outputs a buffered version of the clock applied at the PCLK input. All local bus signals are generated

and sampled from this clock. This output is tri-stated when the local bus is in configuration mode (LMS = 1). It

can be disabled in the PCI bridge mode through the LBBMC register.

Signal Name:

LCS

Signal Description:

Local Bus Chip Select (Configuration Mode Only)

Signal Type:

Input

This active-low signal must be asserted for the device to accept a read or write command from an external host.

This signal is ignored in the PCI bridge mode (LMS = 0) and should be connected high.

DS31256 数据表(PDF) 21 Page - Maxim Integrated Products

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DS31256 数据表(PDF) 21 Page - Maxim Integrated Products

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