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DS31256 数据表(PDF) 32 Page - Maxim Integrated Products |
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DS31256 数据表(HTML) 32 Page - Maxim Integrated Products |
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32 / 183 page  DS31256 256-Channel, High-Throughput HDLC Controller 32 of 183 5. GENERAL DEVICE CONFIGURATION AND STATUS/INTERRUPT 5.1 Master Reset and ID Register Description The master reset and ID (MRID) register can be used to globally reset the device. When the RST bit is set to 1, all the internal registers (except the PCI configuration registers) are placed into their default state, which is 0000h. The host must set the RST bit back to 0 before the device can be programmed for normal operation. The RST bit does not force the PCI outputs to tri-state as does the hardware reset, which is invoked by the PRST pin. A reset invoked by the PRST pin forces the RST bit to 0 as well as the rest of the internal configuration registers. See Section 2 for more details about device initialization. The upper byte of the MRID register is read-only and it can be read by the host to determine the chip revision. Contact the factory for specifics on the meaning of the value read from the ID0 to ID7 bits. Register Name: MRID Register Description: Master Reset and ID Register Register Address: 0000h Bit # 7 6 5 4 3 2 1 0 Name n/a n/a n/a n/a n/a n/a n/a RST Default 0 0 0 0 0 0 0 0 Bit # 15 14 13 12 11 10 9 8 Name ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Default 0 0 0 0 0 0 0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Master Software Reset (RST) 0 = normal operation 1 = force all internal registers (except LBBMC) to their default value of 0000h Bits 8 to 15/Chip Revision ID Bit 0 to 7 (ID0 to ID7). Read-only. Contact the factory for details on the meaning of the ID bits. 5.2 Master Configuration Register Description The master configuration (MC) register is used by the host to enable the receive and transmit DMAs as well as to control their PCI bus bursting attributes and select which port the BERT is dedicated to. Register Name: MC Register Description: Master Configuration Register Register Address: 0010h Bit # 7 6 5 4 3 2 1 0 Name BPS0 PBO TDT1 TDT0 TDE RDT1 DT0 RDE Default 0 0 0 0 0 0 0 0 Bit # 15 14 13 12 11 10 9 8 Name TFPC1 TFPC0 RFPC1 RFPC0 BPS4 BPS3 BPS2 BPS1 Default 0 0 0 0 0 0 0 0 Note: Bits that are underlined are read-only; all other bits are read-write. |
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