Data Sheet

ADP1851

Rev. B | Page 11 of 24

THEORY OF OPERATION

The ADP1851 is a fixed frequency, step-down, synchronous

switching controller with integrated drivers and bootstrapping

for external N-channel power MOSFETs. The current mode

control loop can also be configured to voltage mode. The

controller can be set to operate in pulse skip mode for power

saving at light loads or in forced PWM mode. The ADP1851

includes programmable soft start, output overvoltage

protection, programmable current limit, power good, and

tracking functions. The controller can operate at a switching

frequency between 200 kHz and 1.5 MHz that is programmed

with a resistor or synchronized to an external clock.

CONTROL ARCHITECTURE

The ADP1851 is based on a fixed frequency, emulated peak

current mode, PWM control architecture. The inductor current

is sensed by the voltage drop measured across the external low-

between the low-side MOSFET source and the power ground.

The current is sensed during the off period of the switching

cycle and is conditioned with the internal current sense

amplifier.

The gain of the current sense amplifier is programmable to

3 V/V, 6 V/V, or 12 V/V during the controller power-up

initialization before the device starts switching. A 47 kΩ resistor

between DL and PGND programs a gain of 3 V/V; a 22 kΩ

resistor sets a gain of 6 V/V. Without a resistor, the gain is

programmed to 12 V/V.

The output signal of the current sense amplifier is held, added

to the emulated current ramp in the next switching cycle during

the DH on time, and fed into the PWM comparator, as shown

in Figure 16. This signal is compared with the COMP signal

from the error amplifier and resets the flip-flop, which

generates the PWM pulse. If voltage mode control is selected by

placing a 100 kΩ resistor between DL and PGND, the emulated

current ramp is fed to the PWM comparator without adding the

current sense signal.

FF

OSC

Q

Q

R

S

FROM

ERROR AMP

TO

DRIVERS

SW

PGND

Figure 16. Simplified Control Architecture

As shown in Figure 16, the emulated current ramp is generated

inside the IC, but offers programmability through the RAMP

pin. Selecting an appropriate value resistor to connect between

Control logic enforces antishoot-through operation to limit

cross-conduction of the internal drivers and external MOSFETs.

OSCILLATOR FREQUENCY

The internal oscillator frequency, which ranges from 200 kHz

graphical relationship is shown in Figure 17. For example,

a 78.7 kΩ resistor sets the oscillator frequency to 800 kHz.

Connecting FREQ to AGND or FREQ to VCCO sets the oscil-

lator frequency to 300 kHz or 600 kHz, respectively. For other

empirical formula to calculate these values:

065

.

1

)

kHz

(

568

,

96

)

kΩ

(

−

×

=

OSC

FREQ

f

R

Table 4. Setting the Oscillator Frequency

332 kΩ

200 kHz

78.7 kΩ

800 kHz

60.4 kΩ

1000 kHz

51 kΩ

1200 kHz

40.2 kΩ

1500 kHz

FREQ to AGND

300 kHz

FREQ to VCCO

600 kHz

410

360

310

260

210

160

110

60

10

100

400

700

1000

1300

1600

1900