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ADP1851ACPZ-R7 数据表(PDF) 18 Page - Analog Devices

部件名 ADP1851ACPZ-R7
功能描述  Wide Range Input, Synchronous, Step-Down DC-to-DC Controller
PDF  24 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP1851ACPZ-R7 数据表(HTML) 18 Page - Analog Devices

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ADP1851
Data Sheet
Rev. B | Page 18 of 24
There is also additional power loss during the time, known as
dead time, between the turn-off of the high-side switch and the
turn-on of the low-side switch, when the body diode of the low-
side MOSFET conducts the output current. The power loss in
the body diode is given by
O
SW
D
F
BODYDIODE
I
f
t
V
P
×
×
×
=
where:
VF is the forward voltage drop of the body diode, typically 0.7 V.
tD is the dead time in the ADP1851, typically 25 ns when
driving a medium size MOSFET with input capacitance, CISS,
of approximately 3 nF. The dead time is not fixed. Its effective
value varies with gate drive resistance and CISS; therefore,
PBODYDIODE increases in high load current designs and low voltage
designs.
Therefore, the power loss in the low-side MOSFET is
BODYDIODE
CLS
LS
P
P
P
+
=
Note that the MOSFET on resistance, RDSON, increases with
increasing temperature, with a typical temperature coefficient of
0.4%/°C. The MOSFET junction temperature (TJ) rise over the
ambient temperature is
TJ = TA + θJA × PD
where:
TA is the ambient temperature.
θJA is the thermal resistance of the MOSFET package.
PD is the total power dissipated in the MOSFET.
LOOP COMPENSATION—VOLTAGE MODE
Set the controller to voltage mode operation by placing a
100 kΩ resistor between DL and PGND. Choose the largest
possible ramp amplitude for the voltage mode below 1.5 V.
The ramp voltage is programmed by a resistor placed between
VIN and the RAMP pin as follows:
RAMP
SW
IN
RAMP
V
f
V
R
×
×
=
pF
100
V
2
.
0
The voltage at the RAMP pin is fixed at 0.2 V, and the current
going into RAMP should be between 10 µA and 160 µA. Make
sure that the following condition is satisfied:
μA
160
V
2
.
0
μA
10
RAMP
IN
R
V
(3)
For example, with an input voltage of 12 V, RRAMP should not be
less than 73.8 kΩ.
Assuming that the LC filter design is complete, the feedback control
system can be compensated. In general, aluminum electrolytic
capacitors have high ESR; however, if several aluminum electrolytic
capacitors are connected in parallel and produce a low effective
ESR, then Type III compensation is needed. In addition, ceramic
capacitors have very low ESR (only a few milliohms), making
Type III compensation a better choice.
Type III Compensation
G
(dB)
PHASE
–90°
–270°
fZ
fP
CHF
CI
RZ
RFF
RTOP
RBOT
VOUT
INTERNAL
VREF
EA
FB
COMP
–1
SL
OPE
–1
SL
OPE
CFF
+1
SL
OPE
Figure 26. Type III Compensation
If the output capacitor ESR zero frequency is greater than one-
half of the crossover frequency, use the Type III compensator as
shown in Figure 26.
Calculate the output LC filter resonant frequency as follows:
LC
π
fLC
2
1
=
(4)
Choose a crossover frequency that is 1/10 of the switching
frequency:
10
SW
CO
f
f =
(5)
Set the poles and zeros as follows:
SW
P2
P1
f
f
f
2
1
=
=
(6)
I
Z
SW
CO
Z2
Z1
C
R
f
f
f
f
π
2
1
40
4
=
=
=
=
(7)
or
I
Z
LC
Z2
Z1
C
R
f
f
f
π
2
1
2
=
=
=
(8)
Use the lower zero frequency from Equation 7 or Equation 8.
Calculate the compensation resistor, RZ, as follows:
2
LC
IN
CO
Z1
RAMP
TOP
Z
f
V
f
f
V
R
R =
(9)
Next, calculate CI.
Z1
Z
I
f
R
C
π
=
2
1
(10)
Because of the finite output current drive of the error amplifier,
CI must be less than 10 nF. If it is larger than 10 nF, choose a
larger RTOP and recalculate RZ and CI until CI is less than 10 nF.



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